| Line 43... |
Line 43... |
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entity neorv32_cpu_bus is
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entity neorv32_cpu_bus is
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generic (
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generic (
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CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
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CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
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-- Physical memory protection (PMP) --
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-- Physical memory protection (PMP) --
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PMP_USE : boolean := false; -- implement physical memory protection?
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PMP_USE : boolean := false -- implement physical memory protection?
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PMP_NUM_REGIONS : natural := 4; -- number of regions (1..4)
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PMP_GRANULARITY : natural := 16 -- granularity (1=8B, 2=16B, 3=32B, ...)
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);
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);
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
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rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
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| Line 108... |
Line 106... |
constant pmp_off_mode_c : std_ulogic_vector(1 downto 0) := "00"; -- null region (disabled)
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constant pmp_off_mode_c : std_ulogic_vector(1 downto 0) := "00"; -- null region (disabled)
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--constant pmp_tor_mode_c : std_ulogic_vector(1 downto 0) := "01"; -- top of range
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--constant pmp_tor_mode_c : std_ulogic_vector(1 downto 0) := "01"; -- top of range
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--constant pmp_na4_mode_c : std_ulogic_vector(1 downto 0) := "10"; -- naturally aligned four-byte region
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--constant pmp_na4_mode_c : std_ulogic_vector(1 downto 0) := "10"; -- naturally aligned four-byte region
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constant pmp_napot_mode_c : std_ulogic_vector(1 downto 0) := "11"; -- naturally aligned power-of-two region (>= 8 bytes)
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constant pmp_napot_mode_c : std_ulogic_vector(1 downto 0) := "11"; -- naturally aligned power-of-two region (>= 8 bytes)
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-- PMP granularity --
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constant pmp_g_c : natural := index_size_f(pmp_min_granularity_c);
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-- PMP configuration register bits --
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-- PMP configuration register bits --
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constant pmp_cfg_r_c : natural := 0; -- read permit
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constant pmp_cfg_r_c : natural := 0; -- read permit
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constant pmp_cfg_w_c : natural := 1; -- write permit
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constant pmp_cfg_w_c : natural := 1; -- write permit
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constant pmp_cfg_x_c : natural := 2; -- execute permit
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constant pmp_cfg_x_c : natural := 2; -- execute permit
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constant pmp_cfg_al_c : natural := 3; -- mode bit low
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constant pmp_cfg_al_c : natural := 3; -- mode bit low
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| Line 138... |
Line 139... |
timeout : std_ulogic_vector(index_size_f(bus_timeout_c)-1 downto 0);
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timeout : std_ulogic_vector(index_size_f(bus_timeout_c)-1 downto 0);
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end record;
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end record;
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signal i_arbiter, d_arbiter : bus_arbiter_t;
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signal i_arbiter, d_arbiter : bus_arbiter_t;
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-- physical memory protection --
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-- physical memory protection --
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type pmp_addr34_t is array (0 to PMP_NUM_REGIONS-1) of std_ulogic_vector(data_width_c+1 downto 0);
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type pmp_addr_t is array (0 to pmp_num_regions_c-1) of std_ulogic_vector(data_width_c-1 downto 0);
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type pmp_addr_t is array (0 to PMP_NUM_REGIONS-1) of std_ulogic_vector(data_width_c-1 downto 0);
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type pmp_t is record
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type pmp_t is record
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addr_mask : pmp_addr34_t; -- 34-bit physical address
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addr_mask : pmp_addr_t;
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region_base : pmp_addr_t; -- masked region base address for comparator
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region_base : pmp_addr_t; -- region config base address
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region_i_addr : pmp_addr_t; -- masked instruction access base address for comparator
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region_i_addr : pmp_addr_t; -- masked instruction access base address for comparator
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region_d_addr : pmp_addr_t; -- masked data access base address for comparator
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region_d_addr : pmp_addr_t; -- masked data access base address for comparator
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i_match : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region match for instruction interface
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i_match : std_ulogic_vector(pmp_num_regions_c-1 downto 0); -- region match for instruction interface
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d_match : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region match for data interface
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d_match : std_ulogic_vector(pmp_num_regions_c-1 downto 0); -- region match for data interface
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if_fault : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region access fault for fetch operation
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if_fault : std_ulogic_vector(pmp_num_regions_c-1 downto 0); -- region access fault for fetch operation
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ld_fault : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region access fault for load operation
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ld_fault : std_ulogic_vector(pmp_num_regions_c-1 downto 0); -- region access fault for load operation
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st_fault : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region access fault for store operation
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st_fault : std_ulogic_vector(pmp_num_regions_c-1 downto 0); -- region access fault for store operation
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end record;
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end record;
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signal pmp : pmp_t;
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signal pmp : pmp_t;
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-- pmp faults anybody? --
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-- pmp faults anybody? --
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signal if_pmp_fault : std_ulogic; -- pmp instruction access fault
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signal if_pmp_fault : std_ulogic; -- pmp instruction access fault
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| Line 200... |
Line 200... |
-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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mem_do_reg: process(clk_i)
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mem_do_reg: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if (ctrl_i(ctrl_bus_mo_we_c) = '1') then
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if (ctrl_i(ctrl_bus_mo_we_c) = '1') then
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mdo <= wdata_i; -- memory data out register (MDO)
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mdo <= wdata_i; -- memory data output register (MDO)
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end if;
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end if;
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end if;
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end if;
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end process mem_do_reg;
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end process mem_do_reg;
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-- byte enable and output data alignment --
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-- byte enable and output data alignment --
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| Line 241... |
Line 241... |
-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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mem_out_buf: process(clk_i)
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mem_out_buf: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if (ctrl_i(ctrl_bus_mi_we_c) = '1') then
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if (ctrl_i(ctrl_bus_mi_we_c) = '1') then
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mdi <= d_bus_rdata; -- memory data in register (MDI)
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mdi <= d_bus_rdata; -- memory data input register (MDI)
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end if;
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end if;
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end if;
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end if;
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end process mem_out_buf;
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end process mem_out_buf;
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-- input data alignment and sign extension --
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-- input data alignment and sign extension --
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| Line 293... |
Line 293... |
d_arbiter.err_bus <= '0';
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d_arbiter.err_bus <= '0';
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d_arbiter.timeout <= std_ulogic_vector(to_unsigned(bus_timeout_c, index_size_f(bus_timeout_c)));
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d_arbiter.timeout <= std_ulogic_vector(to_unsigned(bus_timeout_c, index_size_f(bus_timeout_c)));
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else -- in progress
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else -- in progress
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d_arbiter.timeout <= std_ulogic_vector(unsigned(d_arbiter.timeout) - 1);
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d_arbiter.timeout <= std_ulogic_vector(unsigned(d_arbiter.timeout) - 1);
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d_arbiter.err_align <= (d_arbiter.err_align or d_misaligned) and (not ctrl_i(ctrl_bus_derr_ack_c));
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d_arbiter.err_align <= (d_arbiter.err_align or d_misaligned) and (not ctrl_i(ctrl_bus_derr_ack_c));
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d_arbiter.err_bus <= (d_arbiter.err_bus or (not or_all_f(d_arbiter.timeout)) or d_bus_err_i) and (not ctrl_i(ctrl_bus_derr_ack_c));
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d_arbiter.err_bus <= (d_arbiter.err_bus or (not or_all_f(d_arbiter.timeout)) or d_bus_err_i or
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(st_pmp_fault and d_arbiter.wr_req) or (ld_pmp_fault and d_arbiter.rd_req)) and (not ctrl_i(ctrl_bus_derr_ack_c));
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if (d_bus_ack_i = '1') or (ctrl_i(ctrl_bus_derr_ack_c) = '1') then -- wait for normal termination / CPU abort
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if (d_bus_ack_i = '1') or (ctrl_i(ctrl_bus_derr_ack_c) = '1') then -- wait for normal termination / CPU abort
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d_arbiter.wr_req <= '0';
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d_arbiter.wr_req <= '0';
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d_arbiter.rd_req <= '0';
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d_arbiter.rd_req <= '0';
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end if;
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end if;
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end if;
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end if;
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| Line 344... |
Line 345... |
i_arbiter.err_bus <= '0';
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i_arbiter.err_bus <= '0';
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i_arbiter.timeout <= std_ulogic_vector(to_unsigned(bus_timeout_c, index_size_f(bus_timeout_c)));
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i_arbiter.timeout <= std_ulogic_vector(to_unsigned(bus_timeout_c, index_size_f(bus_timeout_c)));
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else -- in progress
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else -- in progress
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i_arbiter.timeout <= std_ulogic_vector(unsigned(i_arbiter.timeout) - 1);
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i_arbiter.timeout <= std_ulogic_vector(unsigned(i_arbiter.timeout) - 1);
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i_arbiter.err_align <= (i_arbiter.err_align or i_misaligned) and (not ctrl_i(ctrl_bus_ierr_ack_c));
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i_arbiter.err_align <= (i_arbiter.err_align or i_misaligned) and (not ctrl_i(ctrl_bus_ierr_ack_c));
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i_arbiter.err_bus <= (i_arbiter.err_bus or (not or_all_f(i_arbiter.timeout)) or i_bus_err_i) and (not ctrl_i(ctrl_bus_ierr_ack_c));
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i_arbiter.err_bus <= (i_arbiter.err_bus or (not or_all_f(i_arbiter.timeout)) or i_bus_err_i or if_pmp_fault) and (not ctrl_i(ctrl_bus_ierr_ack_c));
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if (i_bus_ack_i = '1') or (ctrl_i(ctrl_bus_ierr_ack_c) = '1') then -- wait for normal termination / CPU abort
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if (i_bus_ack_i = '1') or (ctrl_i(ctrl_bus_ierr_ack_c) = '1') then -- wait for normal termination / CPU abort
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i_arbiter.rd_req <= '0';
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i_arbiter.rd_req <= '0';
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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| Line 366... |
Line 367... |
ma_instr_o <= i_arbiter.err_align;
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ma_instr_o <= i_arbiter.err_align;
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be_instr_o <= i_arbiter.err_bus;
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be_instr_o <= i_arbiter.err_bus;
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-- instruction bus (read-only) --
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-- instruction bus (read-only) --
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i_bus_addr_o <= fetch_pc_i(data_width_c-1 downto 2) & "00"; -- instruction access is always 4-byte aligned (even for compressed instructions)
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i_bus_addr_o <= fetch_pc_i(data_width_c-1 downto 2) & "00"; -- instruction access is always 4-byte aligned (even for compressed instructions)
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i_bus_wdata_o <= (others => '0');
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i_bus_wdata_o <= (others => '0'); -- instruction fetch is read-only
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i_bus_ben_o <= (others => '0');
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i_bus_ben_o <= (others => '0');
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i_bus_we_o <= '0';
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i_bus_we_o <= '0';
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i_bus_re_o <= ctrl_i(ctrl_bus_if_c) and (not i_misaligned) and (not if_pmp_fault); -- no actual read when misaligned or PMP fault
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i_bus_re_o <= ctrl_i(ctrl_bus_if_c) and (not i_misaligned) and (not if_pmp_fault); -- no actual read when misaligned or PMP fault
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i_bus_fence_o <= ctrl_i(ctrl_bus_fencei_c);
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i_bus_fence_o <= ctrl_i(ctrl_bus_fencei_c);
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instr_o <= i_bus_rdata_i;
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instr_o <= i_bus_rdata_i;
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| Line 382... |
Line 383... |
'1' when (fetch_pc_i(1) = '1') else '0'; -- 32-bit accesses only
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'1' when (fetch_pc_i(1) = '1') else '0'; -- 32-bit accesses only
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-- Physical Memory Protection (PMP) -------------------------------------------------------
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-- Physical Memory Protection (PMP) -------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- compute address masks --
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-- compute address masks (ITERATIVE!!!) --
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pmp_masks: process(clk_i)
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pmp_masks: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then -- address configuration (not the actual address check!) has a latency of +1 cycles
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if rising_edge(clk_i) then -- address mask computation (not the actual address check!) has a latency of max +32 cycles
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for r in 0 to PMP_NUM_REGIONS-1 loop -- iterate over all regions
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for r in 0 to pmp_num_regions_c-1 loop -- iterate over all regions
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pmp.addr_mask(r) <= (others => '0'); -- default
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pmp.addr_mask(r) <= (others => '0');
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for i in PMP_GRANULARITY+1 to 33 loop
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for i in pmp_g_c to data_width_c-1 loop
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if (i = PMP_GRANULARITY+1) then
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pmp.addr_mask(r)(i) <= pmp.addr_mask(r)(i-1) or (not pmp_addr_i(r)(i-1));
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pmp.addr_mask(r)(i) <= '0';
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else -- current bit = not AND(all previous bits)
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pmp.addr_mask(r)(i) <= not and_all_f(pmp_addr_i(r)(i-1 downto PMP_GRANULARITY));
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end if;
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end loop; -- i
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end loop; -- i
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end loop; -- r
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end loop; -- r
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end if;
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end if;
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end process pmp_masks;
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end process pmp_masks;
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-- compute operands for comparator --
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-- address access check --
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pmp_prepare_check:
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pmp_address_check:
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for r in 0 to PMP_NUM_REGIONS-1 generate -- iterate over all regions
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for r in 0 to pmp_num_regions_c-1 generate -- iterate over all regions
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-- ignore lowest 3 bits of access addresses -> minimal region size = 8 bytes
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pmp.region_i_addr(r) <= fetch_pc_i and pmp.addr_mask(r);
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pmp.region_i_addr(r) <= (fetch_pc_i(31 downto 3) & "000") and pmp.addr_mask(r)(33 downto 2);
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pmp.region_d_addr(r) <= mar and pmp.addr_mask(r);
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pmp.region_d_addr(r) <= (mar(31 downto 3) & "000") and pmp.addr_mask(r)(33 downto 2);
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pmp.region_base(r) <= pmp_addr_i(r)(data_width_c+1 downto 2) and pmp.addr_mask(r);
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pmp.region_base(r) <= pmp_addr_i(r)(33 downto 2) and pmp.addr_mask(r)(33 downto 2);
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--
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pmp.i_match(r) <= '1' when (pmp.region_i_addr(r)(data_width_c-1 downto pmp_g_c) = pmp.region_base(r)(data_width_c-1 downto pmp_g_c)) else '0';
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pmp.d_match(r) <= '1' when (pmp.region_d_addr(r)(data_width_c-1 downto pmp_g_c) = pmp.region_base(r)(data_width_c-1 downto pmp_g_c)) else '0';
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end generate; -- r
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end generate; -- r
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-- check for access address match --
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pmp_addr_check: process (pmp)
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begin
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for r in 0 to PMP_NUM_REGIONS-1 loop -- iterate over all regions
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-- instruction interface --
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pmp.i_match(r) <= '0';
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if (pmp.region_i_addr(r)(31 downto PMP_GRANULARITY+2) = pmp.region_base(r)(31 downto PMP_GRANULARITY+2)) then
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pmp.i_match(r) <= '1';
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end if;
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-- data interface --
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pmp.d_match(r) <= '0';
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if (pmp.region_d_addr(r)(31 downto PMP_GRANULARITY+2) = pmp.region_base(r)(31 downto PMP_GRANULARITY+2)) then
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pmp.d_match(r) <= '1';
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end if;
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end loop; -- r
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end process pmp_addr_check;
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-- check access type and regions's permissions --
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-- check access type and regions's permissions --
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pmp_check_permission: process(pmp, pmp_ctrl_i, ctrl_i)
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pmp_check_permission: process(pmp, pmp_ctrl_i, ctrl_i)
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begin
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begin
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for r in 0 to PMP_NUM_REGIONS-1 loop -- iterate over all regions
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for r in 0 to pmp_num_regions_c-1 loop -- iterate over all regions
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if ((ctrl_i(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c) = priv_mode_u_c) or (pmp_ctrl_i(r)(pmp_cfg_l_c) = '1')) and -- user privilege level or locked pmp entry -> enforce permissions also for machine mode
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if ((ctrl_i(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c) = priv_mode_u_c) or (pmp_ctrl_i(r)(pmp_cfg_l_c) = '1')) and -- user privilege level or locked pmp entry -> enforce permissions also for machine mode
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(pmp_ctrl_i(r)(pmp_cfg_ah_c downto pmp_cfg_al_c) /= pmp_off_mode_c) then -- active entry
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(pmp_ctrl_i(r)(pmp_cfg_ah_c downto pmp_cfg_al_c) /= pmp_off_mode_c) then -- active entry
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pmp.if_fault(r) <= pmp.i_match(r) and (not pmp_ctrl_i(r)(pmp_cfg_x_c)); -- fetch access match no execute permission
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pmp.if_fault(r) <= pmp.i_match(r) and (not pmp_ctrl_i(r)(pmp_cfg_x_c)); -- fetch access match no execute permission
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pmp.ld_fault(r) <= pmp.d_match(r) and (not pmp_ctrl_i(r)(pmp_cfg_r_c)); -- load access match no read permission
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pmp.ld_fault(r) <= pmp.d_match(r) and (not pmp_ctrl_i(r)(pmp_cfg_r_c)); -- load access match no read permission
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pmp.st_fault(r) <= pmp.d_match(r) and (not pmp_ctrl_i(r)(pmp_cfg_w_c)); -- store access match no write permission
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pmp.st_fault(r) <= pmp.d_match(r) and (not pmp_ctrl_i(r)(pmp_cfg_w_c)); -- store access match no write permission
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