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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # Instruction and data bus interfaces and physical memory protection (PMP). #
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-- # Instruction and data bus interfaces and physical memory protection (PMP). #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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entity neorv32_cpu_bus is
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entity neorv32_cpu_bus is
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generic (
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generic (
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CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
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CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
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-- Physical memory protection (PMP) --
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-- Physical memory protection (PMP) --
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PMP_USE : boolean := false; -- implement physical memory protection?
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PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
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PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
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-- Bus Timeout --
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-- Bus Timeout --
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BUS_TIMEOUT : natural := 63 -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
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BUS_TIMEOUT : natural := 63 -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
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);
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);
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port (
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port (
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-- global control --
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-- global control --
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--constant pmp_tor_mode_c : std_ulogic_vector(1 downto 0) := "01"; -- top of range
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--constant pmp_tor_mode_c : std_ulogic_vector(1 downto 0) := "01"; -- top of range
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--constant pmp_na4_mode_c : std_ulogic_vector(1 downto 0) := "10"; -- naturally aligned four-byte region
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--constant pmp_na4_mode_c : std_ulogic_vector(1 downto 0) := "10"; -- naturally aligned four-byte region
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constant pmp_napot_mode_c : std_ulogic_vector(1 downto 0) := "11"; -- naturally aligned power-of-two region (>= 8 bytes)
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constant pmp_napot_mode_c : std_ulogic_vector(1 downto 0) := "11"; -- naturally aligned power-of-two region (>= 8 bytes)
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-- PMP granularity --
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-- PMP granularity --
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constant pmp_g_c : natural := index_size_f(pmp_min_granularity_c);
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constant pmp_g_c : natural := index_size_f(PMP_MIN_GRANULARITY);
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-- PMP configuration register bits --
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-- PMP configuration register bits --
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constant pmp_cfg_r_c : natural := 0; -- read permit
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constant pmp_cfg_r_c : natural := 0; -- read permit
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constant pmp_cfg_w_c : natural := 1; -- write permit
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constant pmp_cfg_w_c : natural := 1; -- write permit
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constant pmp_cfg_x_c : natural := 2; -- execute permit
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constant pmp_cfg_x_c : natural := 2; -- execute permit
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timeout : std_ulogic_vector(index_size_f(BUS_TIMEOUT)-1 downto 0);
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timeout : std_ulogic_vector(index_size_f(BUS_TIMEOUT)-1 downto 0);
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end record;
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end record;
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signal i_arbiter, d_arbiter : bus_arbiter_t;
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signal i_arbiter, d_arbiter : bus_arbiter_t;
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-- physical memory protection --
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-- physical memory protection --
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type pmp_addr_t is array (0 to pmp_num_regions_c-1) of std_ulogic_vector(data_width_c-1 downto 0);
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type pmp_addr_t is array (0 to PMP_NUM_REGIONS-1) of std_ulogic_vector(data_width_c-1 downto 0);
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type pmp_t is record
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type pmp_t is record
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addr_mask : pmp_addr_t;
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addr_mask : pmp_addr_t;
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region_base : pmp_addr_t; -- region config base address
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region_base : pmp_addr_t; -- region config base address
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region_i_addr : pmp_addr_t; -- masked instruction access base address for comparator
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region_i_addr : pmp_addr_t; -- masked instruction access base address for comparator
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region_d_addr : pmp_addr_t; -- masked data access base address for comparator
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region_d_addr : pmp_addr_t; -- masked data access base address for comparator
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i_match : std_ulogic_vector(pmp_num_regions_c-1 downto 0); -- region match for instruction interface
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i_match : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region match for instruction interface
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d_match : std_ulogic_vector(pmp_num_regions_c-1 downto 0); -- region match for data interface
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d_match : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region match for data interface
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if_fault : std_ulogic_vector(pmp_num_regions_c-1 downto 0); -- region access fault for fetch operation
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if_fault : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region access fault for fetch operation
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ld_fault : std_ulogic_vector(pmp_num_regions_c-1 downto 0); -- region access fault for load operation
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ld_fault : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region access fault for load operation
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st_fault : std_ulogic_vector(pmp_num_regions_c-1 downto 0); -- region access fault for store operation
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st_fault : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region access fault for store operation
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end record;
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end record;
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signal pmp : pmp_t;
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signal pmp : pmp_t;
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-- pmp faults anybody? --
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-- pmp faults anybody? --
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signal if_pmp_fault : std_ulogic; -- pmp instruction access fault
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signal if_pmp_fault : std_ulogic; -- pmp instruction access fault
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- compute address masks (ITERATIVE!!!) --
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-- compute address masks (ITERATIVE!!!) --
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pmp_masks: process(clk_i)
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pmp_masks: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then -- address mask computation (not the actual address check!) has a latency of max +32 cycles
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if rising_edge(clk_i) then -- address mask computation (not the actual address check!) has a latency of max +32 cycles
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for r in 0 to pmp_num_regions_c-1 loop -- iterate over all regions
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for r in 0 to PMP_NUM_REGIONS-1 loop -- iterate over all regions
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pmp.addr_mask(r) <= (others => '0');
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pmp.addr_mask(r) <= (others => '0');
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for i in pmp_g_c to data_width_c-1 loop
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for i in pmp_g_c to data_width_c-1 loop
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pmp.addr_mask(r)(i) <= pmp.addr_mask(r)(i-1) or (not pmp_addr_i(r)(i-1));
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pmp.addr_mask(r)(i) <= pmp.addr_mask(r)(i-1) or (not pmp_addr_i(r)(i-1));
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end loop; -- i
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end loop; -- i
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end loop; -- r
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end loop; -- r
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end process pmp_masks;
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end process pmp_masks;
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-- address access check --
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-- address access check --
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pmp_address_check:
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pmp_address_check:
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for r in 0 to pmp_num_regions_c-1 generate -- iterate over all regions
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for r in 0 to PMP_NUM_REGIONS-1 generate -- iterate over all regions
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pmp.region_i_addr(r) <= fetch_pc_i and pmp.addr_mask(r);
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pmp.region_i_addr(r) <= fetch_pc_i and pmp.addr_mask(r);
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pmp.region_d_addr(r) <= mar and pmp.addr_mask(r);
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pmp.region_d_addr(r) <= mar and pmp.addr_mask(r);
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pmp.region_base(r) <= pmp_addr_i(r)(data_width_c+1 downto 2) and pmp.addr_mask(r);
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pmp.region_base(r) <= pmp_addr_i(r)(data_width_c+1 downto 2) and pmp.addr_mask(r);
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--
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--
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pmp.i_match(r) <= '1' when (pmp.region_i_addr(r)(data_width_c-1 downto pmp_g_c) = pmp.region_base(r)(data_width_c-1 downto pmp_g_c)) else '0';
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pmp.i_match(r) <= '1' when (pmp.region_i_addr(r)(data_width_c-1 downto pmp_g_c) = pmp.region_base(r)(data_width_c-1 downto pmp_g_c)) else '0';
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-- check access type and regions's permissions --
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-- check access type and regions's permissions --
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pmp_check_permission: process(pmp, pmp_ctrl_i, ctrl_i)
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pmp_check_permission: process(pmp, pmp_ctrl_i, ctrl_i)
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begin
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begin
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for r in 0 to pmp_num_regions_c-1 loop -- iterate over all regions
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for r in 0 to PMP_NUM_REGIONS-1 loop -- iterate over all regions
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if ((ctrl_i(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c) = priv_mode_u_c) or (pmp_ctrl_i(r)(pmp_cfg_l_c) = '1')) and -- user privilege level or locked pmp entry -> enforce permissions also for machine mode
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if ((ctrl_i(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c) = priv_mode_u_c) or (pmp_ctrl_i(r)(pmp_cfg_l_c) = '1')) and -- user privilege level or locked pmp entry -> enforce permissions also for machine mode
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(pmp_ctrl_i(r)(pmp_cfg_ah_c downto pmp_cfg_al_c) /= pmp_off_mode_c) then -- active entry
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(pmp_ctrl_i(r)(pmp_cfg_ah_c downto pmp_cfg_al_c) /= pmp_off_mode_c) then -- active entry
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pmp.if_fault(r) <= pmp.i_match(r) and (not pmp_ctrl_i(r)(pmp_cfg_x_c)); -- fetch access match no execute permission
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pmp.if_fault(r) <= pmp.i_match(r) and (not pmp_ctrl_i(r)(pmp_cfg_x_c)); -- fetch access match no execute permission
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pmp.ld_fault(r) <= pmp.d_match(r) and (not pmp_ctrl_i(r)(pmp_cfg_r_c)); -- load access match no read permission
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pmp.ld_fault(r) <= pmp.d_match(r) and (not pmp_ctrl_i(r)(pmp_cfg_r_c)); -- load access match no read permission
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pmp.st_fault(r) <= pmp.d_match(r) and (not pmp_ctrl_i(r)(pmp_cfg_w_c)); -- store access match no write permission
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pmp.st_fault(r) <= pmp.d_match(r) and (not pmp_ctrl_i(r)(pmp_cfg_w_c)); -- store access match no write permission
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end loop; -- r
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end loop; -- r
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end process pmp_check_permission;
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end process pmp_check_permission;
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-- final PMP access fault signals --
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-- final PMP access fault signals --
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if_pmp_fault <= or_all_f(pmp.if_fault) when (PMP_USE = true) else '0';
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if_pmp_fault <= or_all_f(pmp.if_fault) when (PMP_NUM_REGIONS > 0) else '0';
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ld_pmp_fault <= or_all_f(pmp.ld_fault) when (PMP_USE = true) else '0';
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ld_pmp_fault <= or_all_f(pmp.ld_fault) when (PMP_NUM_REGIONS > 0) else '0';
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st_pmp_fault <= or_all_f(pmp.st_fault) when (PMP_USE = true) else '0';
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st_pmp_fault <= or_all_f(pmp.st_fault) when (PMP_NUM_REGIONS > 0) else '0';
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end neorv32_cpu_bus_rtl;
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end neorv32_cpu_bus_rtl;
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