| Line 156... |
Line 156... |
ld_fault : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region access fault for load operation
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ld_fault : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region access fault for load operation
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st_fault : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region access fault for store operation
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st_fault : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region access fault for store operation
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end record;
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end record;
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signal pmp : pmp_t;
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signal pmp : pmp_t;
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-- pmp faults anybody? --
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-- memory control signal buffer (when using PMP) --
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signal d_bus_we, d_bus_we_buf : std_ulogic;
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signal d_bus_re, d_bus_re_buf : std_ulogic;
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signal i_bus_re, i_bus_re_buf : std_ulogic;
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-- pmp faults anyone? --
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signal if_pmp_fault : std_ulogic; -- pmp instruction access fault
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signal if_pmp_fault : std_ulogic; -- pmp instruction access fault
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signal ld_pmp_fault : std_ulogic; -- pmp load access fault
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signal ld_pmp_fault : std_ulogic; -- pmp load access fault
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signal st_pmp_fault : std_ulogic; -- pmp store access fault
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signal st_pmp_fault : std_ulogic; -- pmp store access fault
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begin
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begin
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-- Sanity Checks --------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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assert not (PMP_NUM_REGIONS > pmp_num_regions_critical_c) report "NEORV32 CPU CONFIG WARNING! Number of implemented PMP regions (PMP_NUM_REGIONS = " & integer'image(PMP_NUM_REGIONS) & ") beyond critical limit (pmp_num_regions_critical_c = " & integer'image(pmp_num_regions_critical_c) & "). Inserting another register stage (that will increase memory latency by +1 cycle)." severity warning;
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-- Data Interface: Access Address ---------------------------------------------------------
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-- Data Interface: Access Address ---------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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mem_adr_reg: process(clk_i)
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mem_adr_reg: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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| Line 322... |
Line 332... |
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-- data bus (read/write)--
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-- data bus (read/write)--
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d_bus_addr_o <= mar;
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d_bus_addr_o <= mar;
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d_bus_wdata_o <= d_bus_wdata;
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d_bus_wdata_o <= d_bus_wdata;
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d_bus_ben_o <= d_bus_ben;
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d_bus_ben_o <= d_bus_ben;
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d_bus_we_o <= ctrl_i(ctrl_bus_wr_c) and (not d_misaligned) and (not st_pmp_fault); -- no actual write when misaligned or PMP fault
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d_bus_we <= ctrl_i(ctrl_bus_wr_c) and (not d_misaligned) and (not st_pmp_fault); -- no actual write when misaligned or PMP fault
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d_bus_re_o <= ctrl_i(ctrl_bus_rd_c) and (not d_misaligned) and (not ld_pmp_fault); -- no actual read when misaligned or PMP fault
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d_bus_re <= ctrl_i(ctrl_bus_rd_c) and (not d_misaligned) and (not ld_pmp_fault); -- no actual read when misaligned or PMP fault
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d_bus_we_o <= d_bus_we_buf when (PMP_NUM_REGIONS > pmp_num_regions_critical_c) else d_bus_we;
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d_bus_re_o <= d_bus_re_buf when (PMP_NUM_REGIONS > pmp_num_regions_critical_c) else d_bus_re;
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d_bus_fence_o <= ctrl_i(ctrl_bus_fence_c);
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d_bus_fence_o <= ctrl_i(ctrl_bus_fence_c);
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d_bus_rdata <= d_bus_rdata_i;
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d_bus_rdata <= d_bus_rdata_i;
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d_bus_lock_o <= ctrl_i(ctrl_bus_lock_c);
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d_bus_lock_o <= ctrl_i(ctrl_bus_lock_c);
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-- additional register stage for control signals if using PMP_NUM_REGIONS > pmp_num_regions_critical_c --
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pmp_dbus_buffer: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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d_bus_we_buf <= '0';
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d_bus_re_buf <= '0';
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elsif rising_edge(clk_i) then
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d_bus_we_buf <= d_bus_we;
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d_bus_re_buf <= d_bus_re;
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end if;
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end process pmp_dbus_buffer;
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-- Instruction Fetch Arbiter --------------------------------------------------------------
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-- Instruction Fetch Arbiter --------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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ifetch_arbiter: process(rstn_i, clk_i)
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ifetch_arbiter: process(rstn_i, clk_i)
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begin
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begin
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| Line 373... |
Line 397... |
-- instruction bus (read-only) --
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-- instruction bus (read-only) --
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i_bus_addr_o <= fetch_pc_i(data_width_c-1 downto 2) & "00"; -- instruction access is always 4-byte aligned (even for compressed instructions)
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i_bus_addr_o <= fetch_pc_i(data_width_c-1 downto 2) & "00"; -- instruction access is always 4-byte aligned (even for compressed instructions)
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i_bus_wdata_o <= (others => '0'); -- instruction fetch is read-only
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i_bus_wdata_o <= (others => '0'); -- instruction fetch is read-only
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i_bus_ben_o <= (others => '0');
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i_bus_ben_o <= (others => '0');
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i_bus_we_o <= '0';
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i_bus_we_o <= '0';
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i_bus_re_o <= ctrl_i(ctrl_bus_if_c) and (not i_misaligned) and (not if_pmp_fault); -- no actual read when misaligned or PMP fault
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i_bus_re <= ctrl_i(ctrl_bus_if_c) and (not i_misaligned) and (not if_pmp_fault); -- no actual read when misaligned or PMP fault
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i_bus_re_o <= i_bus_re_buf when (PMP_NUM_REGIONS > pmp_num_regions_critical_c) else i_bus_re;
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i_bus_fence_o <= ctrl_i(ctrl_bus_fencei_c);
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i_bus_fence_o <= ctrl_i(ctrl_bus_fencei_c);
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instr_o <= i_bus_rdata_i;
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instr_o <= i_bus_rdata_i;
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i_bus_lock_o <= '0'; -- instruction fetch cannot be atomic
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i_bus_lock_o <= '0'; -- instruction fetch cannot be atomic
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-- check instruction access --
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-- check instruction access --
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i_misaligned <= '0' when (CPU_EXTENSION_RISCV_C = true) else -- no alignment exceptions possible when using C-extension
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i_misaligned <= '0' when (CPU_EXTENSION_RISCV_C = true) else -- no alignment exceptions possible when using C-extension
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'1' when (fetch_pc_i(1) = '1') else '0'; -- 32-bit accesses only
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'1' when (fetch_pc_i(1) = '1') else '0'; -- 32-bit accesses only
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-- additional register stage for control signals if using PMP_NUM_REGIONS > pmp_num_regions_critical_c --
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pmp_ibus_buffer: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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i_bus_re_buf <= '0';
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elsif rising_edge(clk_i) then
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i_bus_re_buf <= i_bus_re;
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end if;
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end process pmp_ibus_buffer;
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-- Physical Memory Protection (PMP) -------------------------------------------------------
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-- Physical Memory Protection (PMP) -------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- compute address masks (ITERATIVE!!!) --
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-- compute address masks (ITERATIVE!!!) --
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pmp_masks: process(clk_i)
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pmp_masks: process(clk_i)
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