| Line 45... |
Line 45... |
generic (
|
generic (
|
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
|
-- Physical memory protection (PMP) --
|
-- Physical memory protection (PMP) --
|
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
|
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
|
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
PMP_MIN_GRANULARITY : natural := 64*1024 -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
-- Bus Timeout --
|
|
BUS_TIMEOUT : natural := 63 -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
|
|
);
|
);
|
port (
|
port (
|
-- global control --
|
-- global control --
|
clk_i : in std_ulogic; -- global clock, rising edge
|
clk_i : in std_ulogic; -- global clock, rising edge
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
| Line 68... |
Line 66... |
wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data
|
wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data
|
rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
|
rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
|
mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
|
mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
|
d_wait_o : out std_ulogic; -- wait for access to complete
|
d_wait_o : out std_ulogic; -- wait for access to complete
|
--
|
--
|
bus_excl_ok_o : out std_ulogic; -- bus exclusive access successful
|
excl_state_o : out std_ulogic; -- atomic/exclusive access status
|
ma_load_o : out std_ulogic; -- misaligned load data address
|
ma_load_o : out std_ulogic; -- misaligned load data address
|
ma_store_o : out std_ulogic; -- misaligned store data address
|
ma_store_o : out std_ulogic; -- misaligned store data address
|
be_load_o : out std_ulogic; -- bus error on load data access
|
be_load_o : out std_ulogic; -- bus error on load data access
|
be_store_o : out std_ulogic; -- bus error on store data access
|
be_store_o : out std_ulogic; -- bus error on store data access
|
-- physical memory protection --
|
-- physical memory protection --
|
| Line 83... |
Line 81... |
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
i_bus_we_o : out std_ulogic; -- write enable
|
i_bus_we_o : out std_ulogic; -- write enable
|
i_bus_re_o : out std_ulogic; -- read enable
|
i_bus_re_o : out std_ulogic; -- read enable
|
i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
i_bus_lock_o : out std_ulogic; -- exclusive access request
|
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
i_bus_err_i : in std_ulogic; -- bus transfer error
|
i_bus_err_i : in std_ulogic; -- bus transfer error
|
i_bus_fence_o : out std_ulogic; -- fence operation
|
i_bus_fence_o : out std_ulogic; -- fence operation
|
-- data bus --
|
-- data bus --
|
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
d_bus_we_o : out std_ulogic; -- write enable
|
d_bus_we_o : out std_ulogic; -- write enable
|
d_bus_re_o : out std_ulogic; -- read enable
|
d_bus_re_o : out std_ulogic; -- read enable
|
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
d_bus_lock_o : out std_ulogic; -- exclusive access request
|
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
d_bus_err_i : in std_ulogic; -- bus transfer error
|
d_bus_err_i : in std_ulogic; -- bus transfer error
|
d_bus_fence_o : out std_ulogic; -- fence operation
|
d_bus_fence_o : out std_ulogic -- fence operation
|
d_bus_excl_o : out std_ulogic; -- exclusive access request
|
|
d_bus_excl_i : in std_ulogic -- state of exclusiv access (set if success)
|
|
);
|
);
|
end neorv32_cpu_bus;
|
end neorv32_cpu_bus;
|
|
|
architecture neorv32_cpu_bus_rtl of neorv32_cpu_bus is
|
architecture neorv32_cpu_bus_rtl of neorv32_cpu_bus is
|
|
|
| Line 128... |
Line 124... |
signal mar, mdo, mdi : std_ulogic_vector(data_width_c-1 downto 0);
|
signal mar, mdo, mdi : std_ulogic_vector(data_width_c-1 downto 0);
|
|
|
-- data access --
|
-- data access --
|
signal d_bus_wdata : std_ulogic_vector(data_width_c-1 downto 0); -- write data
|
signal d_bus_wdata : std_ulogic_vector(data_width_c-1 downto 0); -- write data
|
signal d_bus_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- read data
|
signal d_bus_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- read data
|
|
signal rdata_align : std_ulogic_vector(data_width_c-1 downto 0); -- read-data alignment
|
signal d_bus_ben : std_ulogic_vector(3 downto 0); -- write data byte enable
|
signal d_bus_ben : std_ulogic_vector(3 downto 0); -- write data byte enable
|
|
|
-- misaligned access? --
|
-- misaligned access? --
|
signal d_misaligned, i_misaligned : std_ulogic;
|
signal d_misaligned, i_misaligned : std_ulogic;
|
|
|
| Line 139... |
Line 136... |
type bus_arbiter_t is record
|
type bus_arbiter_t is record
|
rd_req : std_ulogic; -- read access in progress
|
rd_req : std_ulogic; -- read access in progress
|
wr_req : std_ulogic; -- write access in progress
|
wr_req : std_ulogic; -- write access in progress
|
err_align : std_ulogic; -- alignment error
|
err_align : std_ulogic; -- alignment error
|
err_bus : std_ulogic; -- bus access error
|
err_bus : std_ulogic; -- bus access error
|
timeout : std_ulogic_vector(index_size_f(BUS_TIMEOUT)-1 downto 0);
|
|
end record;
|
end record;
|
signal i_arbiter, d_arbiter : bus_arbiter_t;
|
signal i_arbiter, d_arbiter : bus_arbiter_t;
|
|
|
|
-- atomic/exclusive access - reservation controller --
|
|
signal exclusive_lock : std_ulogic;
|
|
signal exclusive_lock_status : std_ulogic_vector(data_width_c-1 downto 0); -- read data
|
|
|
-- physical memory protection --
|
-- physical memory protection --
|
type pmp_addr_t is array (0 to PMP_NUM_REGIONS-1) of std_ulogic_vector(data_width_c-1 downto 0);
|
type pmp_addr_t is array (0 to PMP_NUM_REGIONS-1) of std_ulogic_vector(data_width_c-1 downto 0);
|
type pmp_t is record
|
type pmp_t is record
|
addr_mask : pmp_addr_t;
|
addr_mask : pmp_addr_t;
|
region_base : pmp_addr_t; -- region config base address
|
region_base : pmp_addr_t; -- region config base address
|
| Line 256... |
Line 256... |
end process byte_enable;
|
end process byte_enable;
|
|
|
|
|
-- Data Interface: Read Data --------------------------------------------------------------
|
-- Data Interface: Read Data --------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
mem_out_buf: process(rstn_i, clk_i)
|
mem_di_reg: process(rstn_i, clk_i)
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
mdi <= (others => def_rst_val_c);
|
mdi <= (others => def_rst_val_c);
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
if (ctrl_i(ctrl_bus_mi_we_c) = '1') then
|
if (ctrl_i(ctrl_bus_mi_we_c) = '1') then
|
mdi <= d_bus_rdata; -- memory data input register (MDI)
|
mdi <= d_bus_rdata; -- memory data input register (MDI)
|
end if;
|
end if;
|
end if;
|
end if;
|
end process mem_out_buf;
|
end process mem_di_reg;
|
|
|
-- input data alignment and sign extension --
|
-- input data alignment and sign extension --
|
read_align: process(mdi, mar, ctrl_i)
|
read_align: process(mdi, mar, ctrl_i)
|
variable byte_in_v : std_ulogic_vector(07 downto 0);
|
variable byte_in_v : std_ulogic_vector(07 downto 0);
|
variable hword_in_v : std_ulogic_vector(15 downto 0);
|
variable hword_in_v : std_ulogic_vector(15 downto 0);
|
| Line 282... |
Line 282... |
when others => byte_in_v := mdi(31 downto 24); hword_in_v := mdi(31 downto 16); -- byte 3 / half-word 1
|
when others => byte_in_v := mdi(31 downto 24); hword_in_v := mdi(31 downto 16); -- byte 3 / half-word 1
|
end case;
|
end case;
|
-- actual data size --
|
-- actual data size --
|
case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is
|
case ctrl_i(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) is
|
when "00" => -- byte
|
when "00" => -- byte
|
rdata_o(31 downto 08) <= (others => ((not ctrl_i(ctrl_bus_unsigned_c)) and byte_in_v(7))); -- sign extension
|
rdata_align(31 downto 08) <= (others => ((not ctrl_i(ctrl_bus_unsigned_c)) and byte_in_v(7))); -- sign extension
|
rdata_o(07 downto 00) <= byte_in_v;
|
rdata_align(07 downto 00) <= byte_in_v;
|
when "01" => -- half-word
|
when "01" => -- half-word
|
rdata_o(31 downto 16) <= (others => ((not ctrl_i(ctrl_bus_unsigned_c)) and hword_in_v(15))); -- sign extension
|
rdata_align(31 downto 16) <= (others => ((not ctrl_i(ctrl_bus_unsigned_c)) and hword_in_v(15))); -- sign extension
|
rdata_o(15 downto 00) <= hword_in_v; -- high half-word
|
rdata_align(15 downto 00) <= hword_in_v; -- high half-word
|
when others => -- word
|
when others => -- word
|
rdata_o <= mdi; -- full word
|
rdata_align <= mdi; -- full word
|
end case;
|
end case;
|
end process read_align;
|
end process read_align;
|
|
|
|
-- insert exclusive lock status for SC operations only --
|
|
rdata_o <= exclusive_lock_status when (CPU_EXTENSION_RISCV_A = true) and (ctrl_i(ctrl_bus_ch_lock_c) = '1') else rdata_align;
|
|
|
|
|
-- Data Access Arbiter --------------------------------------------------------------------
|
-- Data Access Arbiter --------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
data_access_arbiter: process(rstn_i, clk_i)
|
data_access_arbiter: process(rstn_i, clk_i)
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
d_arbiter.wr_req <= '0';
|
d_arbiter.wr_req <= '0';
|
d_arbiter.rd_req <= '0';
|
d_arbiter.rd_req <= '0';
|
d_arbiter.err_align <= '0';
|
d_arbiter.err_align <= '0';
|
d_arbiter.err_bus <= '0';
|
d_arbiter.err_bus <= '0';
|
d_arbiter.timeout <= (others => '0');
|
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
-- data access request --
|
-- data access request --
|
if (d_arbiter.wr_req = '0') and (d_arbiter.rd_req = '0') then -- idle
|
if (d_arbiter.wr_req = '0') and (d_arbiter.rd_req = '0') then -- idle
|
d_arbiter.wr_req <= ctrl_i(ctrl_bus_wr_c);
|
d_arbiter.wr_req <= ctrl_i(ctrl_bus_wr_c);
|
d_arbiter.rd_req <= ctrl_i(ctrl_bus_rd_c);
|
d_arbiter.rd_req <= ctrl_i(ctrl_bus_rd_c);
|
d_arbiter.err_align <= d_misaligned;
|
d_arbiter.err_align <= d_misaligned;
|
d_arbiter.err_bus <= '0';
|
d_arbiter.err_bus <= '0';
|
d_arbiter.timeout <= std_ulogic_vector(to_unsigned(BUS_TIMEOUT, index_size_f(BUS_TIMEOUT)));
|
|
else -- in progress
|
else -- in progress
|
d_arbiter.timeout <= std_ulogic_vector(unsigned(d_arbiter.timeout) - 1);
|
|
d_arbiter.err_align <= (d_arbiter.err_align or d_misaligned) and (not ctrl_i(ctrl_bus_derr_ack_c));
|
d_arbiter.err_align <= (d_arbiter.err_align or d_misaligned) and (not ctrl_i(ctrl_bus_derr_ack_c));
|
d_arbiter.err_bus <= (d_arbiter.err_bus or (not or_all_f(d_arbiter.timeout)) or d_bus_err_i or
|
d_arbiter.err_bus <= (d_arbiter.err_bus or d_bus_err_i or (st_pmp_fault and d_arbiter.wr_req) or (ld_pmp_fault and d_arbiter.rd_req)) and
|
(st_pmp_fault and d_arbiter.wr_req) or (ld_pmp_fault and d_arbiter.rd_req)) and (not ctrl_i(ctrl_bus_derr_ack_c));
|
(not ctrl_i(ctrl_bus_derr_ack_c));
|
if (d_bus_ack_i = '1') or (ctrl_i(ctrl_bus_derr_ack_c) = '1') then -- wait for normal termination / CPU abort
|
if (d_bus_ack_i = '1') or (ctrl_i(ctrl_bus_derr_ack_c) = '1') then -- wait for normal termination / CPU abort
|
d_arbiter.wr_req <= '0';
|
d_arbiter.wr_req <= '0';
|
d_arbiter.rd_req <= '0';
|
d_arbiter.rd_req <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process data_access_arbiter;
|
end process data_access_arbiter;
|
|
|
-- cancel bus access --
|
|
d_bus_cancel_o <= (d_arbiter.wr_req or d_arbiter.rd_req) and ctrl_i(ctrl_bus_derr_ack_c);
|
|
|
|
-- wait for bus transaction to finish --
|
-- wait for bus transaction to finish --
|
d_wait_o <= (d_arbiter.wr_req or d_arbiter.rd_req) and (not d_bus_ack_i);
|
d_wait_o <= (d_arbiter.wr_req or d_arbiter.rd_req) and (not d_bus_ack_i);
|
|
|
-- output data access error to controller --
|
-- output data access error to controller --
|
ma_load_o <= d_arbiter.rd_req and d_arbiter.err_align;
|
ma_load_o <= d_arbiter.rd_req and d_arbiter.err_align;
|
| Line 346... |
Line 343... |
d_bus_re <= ctrl_i(ctrl_bus_rd_c) and (not d_misaligned) and (not ld_pmp_fault); -- no actual read when misaligned or PMP fault
|
d_bus_re <= ctrl_i(ctrl_bus_rd_c) and (not d_misaligned) and (not ld_pmp_fault); -- no actual read when misaligned or PMP fault
|
d_bus_we_o <= d_bus_we_buf when (PMP_NUM_REGIONS > pmp_num_regions_critical_c) else d_bus_we;
|
d_bus_we_o <= d_bus_we_buf when (PMP_NUM_REGIONS > pmp_num_regions_critical_c) else d_bus_we;
|
d_bus_re_o <= d_bus_re_buf when (PMP_NUM_REGIONS > pmp_num_regions_critical_c) else d_bus_re;
|
d_bus_re_o <= d_bus_re_buf when (PMP_NUM_REGIONS > pmp_num_regions_critical_c) else d_bus_re;
|
d_bus_fence_o <= ctrl_i(ctrl_bus_fence_c);
|
d_bus_fence_o <= ctrl_i(ctrl_bus_fence_c);
|
d_bus_rdata <= d_bus_rdata_i;
|
d_bus_rdata <= d_bus_rdata_i;
|
d_bus_excl_o <= ctrl_i(ctrl_bus_excl_c);
|
|
|
|
-- additional register stage for control signals if using PMP_NUM_REGIONS > pmp_num_regions_critical_c --
|
-- additional register stage for control signals if using PMP_NUM_REGIONS > pmp_num_regions_critical_c --
|
pmp_dbus_buffer: process(rstn_i, clk_i)
|
pmp_dbus_buffer: process(rstn_i, clk_i)
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
| Line 360... |
Line 356... |
d_bus_we_buf <= d_bus_we;
|
d_bus_we_buf <= d_bus_we;
|
d_bus_re_buf <= d_bus_re;
|
d_bus_re_buf <= d_bus_re;
|
end if;
|
end if;
|
end process pmp_dbus_buffer;
|
end process pmp_dbus_buffer;
|
|
|
-- Atomic memory access - status buffer --
|
|
atomic_access_status: process(rstn_i, clk_i)
|
-- Reservation Controller (LR/SC [A extension]) -------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
exclusive_access_controller: process(rstn_i, clk_i)
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
bus_excl_ok_o <= '0';
|
exclusive_lock <= '0';
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
if (CPU_EXTENSION_RISCV_A = true) then
|
if (CPU_EXTENSION_RISCV_A = true) then
|
if (d_bus_ack_i = '1') then
|
if (ctrl_i(ctrl_trap_c) = '1') or (ctrl_i(ctrl_bus_de_lock_c) = '1') then -- remove lock if entering a trap or executing a non-load-reservate memory access
|
bus_excl_ok_o <= d_bus_excl_i; -- set if access was exclusive
|
exclusive_lock <= '0';
|
elsif (d_arbiter.rd_req = '0') and (d_arbiter.wr_req = '0') then -- bus access done
|
elsif (ctrl_i(ctrl_bus_lock_c) = '1') then -- set new lock
|
bus_excl_ok_o <= '0';
|
exclusive_lock <= '1';
|
end if;
|
end if;
|
else
|
else
|
bus_excl_ok_o <= '0';
|
exclusive_lock <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process atomic_access_status;
|
end process exclusive_access_controller;
|
|
|
|
-- lock status for SC operation --
|
|
exclusive_lock_status(data_width_c-1 downto 1) <= (others => '0');
|
|
exclusive_lock_status(0) <= not exclusive_lock;
|
|
|
|
-- output reservation status to control unit (to check if SC should write at all) --
|
|
excl_state_o <= exclusive_lock;
|
|
|
|
-- output to memory system --
|
|
i_bus_lock_o <= '0'; -- instruction fetches cannot be lockes
|
|
d_bus_lock_o <= exclusive_lock;
|
|
|
|
|
-- Instruction Fetch Arbiter --------------------------------------------------------------
|
-- Instruction Fetch Arbiter --------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
ifetch_arbiter: process(rstn_i, clk_i)
|
ifetch_arbiter: process(rstn_i, clk_i)
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
i_arbiter.rd_req <= '0';
|
i_arbiter.rd_req <= '0';
|
i_arbiter.err_align <= '0';
|
i_arbiter.err_align <= '0';
|
i_arbiter.err_bus <= '0';
|
i_arbiter.err_bus <= '0';
|
i_arbiter.timeout <= (others => '0');
|
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
-- instruction fetch request --
|
-- instruction fetch request --
|
if (i_arbiter.rd_req = '0') then -- idle
|
if (i_arbiter.rd_req = '0') then -- idle
|
i_arbiter.rd_req <= ctrl_i(ctrl_bus_if_c);
|
i_arbiter.rd_req <= ctrl_i(ctrl_bus_if_c);
|
i_arbiter.err_align <= i_misaligned;
|
i_arbiter.err_align <= i_misaligned;
|
i_arbiter.err_bus <= '0';
|
i_arbiter.err_bus <= '0';
|
i_arbiter.timeout <= std_ulogic_vector(to_unsigned(BUS_TIMEOUT, index_size_f(BUS_TIMEOUT)));
|
else -- in progres
|
else -- in progress
|
|
i_arbiter.timeout <= std_ulogic_vector(unsigned(i_arbiter.timeout) - 1);
|
|
i_arbiter.err_align <= (i_arbiter.err_align or i_misaligned) and (not ctrl_i(ctrl_bus_ierr_ack_c));
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i_arbiter.err_align <= (i_arbiter.err_align or i_misaligned) and (not ctrl_i(ctrl_bus_ierr_ack_c));
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i_arbiter.err_bus <= (i_arbiter.err_bus or (not or_all_f(i_arbiter.timeout)) or i_bus_err_i or if_pmp_fault) and (not ctrl_i(ctrl_bus_ierr_ack_c));
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i_arbiter.err_bus <= (i_arbiter.err_bus or i_bus_err_i or if_pmp_fault) and (not ctrl_i(ctrl_bus_ierr_ack_c));
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if (i_bus_ack_i = '1') or (ctrl_i(ctrl_bus_ierr_ack_c) = '1') then -- wait for normal termination / CPU abort
|
if (i_bus_ack_i = '1') or (ctrl_i(ctrl_bus_ierr_ack_c) = '1') then -- wait for normal termination / CPU abort
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i_arbiter.rd_req <= '0';
|
i_arbiter.rd_req <= '0';
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end if;
|
end if;
|
end if;
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end if;
|
end if;
|
end if;
|
end process ifetch_arbiter;
|
end process ifetch_arbiter;
|
|
|
i_arbiter.wr_req <= '0'; -- instruction fetch is read-only
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i_arbiter.wr_req <= '0'; -- instruction fetch is read-only
|
|
|
-- cancel bus access --
|
|
i_bus_cancel_o <= i_arbiter.rd_req and ctrl_i(ctrl_bus_ierr_ack_c);
|
|
|
|
-- wait for bus transaction to finish --
|
-- wait for bus transaction to finish --
|
i_wait_o <= i_arbiter.rd_req and (not i_bus_ack_i);
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i_wait_o <= i_arbiter.rd_req and (not i_bus_ack_i);
|
|
|
-- output instruction fetch error to controller --
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-- output instruction fetch error to controller --
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ma_instr_o <= i_arbiter.err_align;
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ma_instr_o <= i_arbiter.err_align;
|
