| Line 149... |
Line 149... |
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-- instruction execution engine --
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-- instruction execution engine --
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type execute_engine_state_t is (SYS_WAIT, DISPATCH, TRAP, EXECUTE, ALU_WAIT, BRANCH, LOADSTORE_0, LOADSTORE_1, LOADSTORE_2, CSR_ACCESS);
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type execute_engine_state_t is (SYS_WAIT, DISPATCH, TRAP, EXECUTE, ALU_WAIT, BRANCH, LOADSTORE_0, LOADSTORE_1, LOADSTORE_2, CSR_ACCESS);
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type execute_engine_t is record
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type execute_engine_t is record
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state : execute_engine_state_t;
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state : execute_engine_state_t;
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state_prev : execute_engine_state_t;
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state_nxt : execute_engine_state_t;
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state_nxt : execute_engine_state_t;
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i_reg : std_ulogic_vector(31 downto 0);
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i_reg : std_ulogic_vector(31 downto 0);
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i_reg_nxt : std_ulogic_vector(31 downto 0);
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i_reg_nxt : std_ulogic_vector(31 downto 0);
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is_ci : std_ulogic; -- current instruction is de-compressed instruction
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is_ci : std_ulogic; -- current instruction is de-compressed instruction
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is_ci_nxt : std_ulogic;
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is_ci_nxt : std_ulogic;
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Line 325... |
fetch_engine.bus_err_ack <= '0';
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fetch_engine.bus_err_ack <= '0';
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-- instruction prefetch buffer interface --
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-- instruction prefetch buffer interface --
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ipb.we <= '0';
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ipb.we <= '0';
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ipb.clear <= '0';
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ipb.clear <= '0';
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ipb.wdata <= '0' & fetch_engine.i_buf2(33 downto 32) & '0' & fetch_engine.i_buf2(31 downto 0);
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ipb.wdata <= (others => '0');
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ipb.waddr <= fetch_engine.pc_real(data_width_c-1 downto 1) & '0';
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ipb.waddr <= fetch_engine.pc_real(data_width_c-1 downto 1) & '0';
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-- state machine --
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-- state machine --
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case fetch_engine.state is
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case fetch_engine.state is
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Line 387... |
if (fetch_engine.i_buf2(17 downto 16) = "11") then -- uncompressed
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if (fetch_engine.i_buf2(17 downto 16) = "11") then -- uncompressed
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ipb.wdata <= '0' & fetch_engine.i_buf(33 downto 32) & '0' & fetch_engine.i_buf(15 downto 00) & fetch_engine.i_buf2(31 downto 16);
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ipb.wdata <= '0' & fetch_engine.i_buf(33 downto 32) & '0' & fetch_engine.i_buf(15 downto 00) & fetch_engine.i_buf2(31 downto 16);
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fetch_engine.pc_real_add <= std_ulogic_vector(to_unsigned(4, data_width_c));
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fetch_engine.pc_real_add <= std_ulogic_vector(to_unsigned(4, data_width_c));
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fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(4, data_width_c));
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fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(4, data_width_c));
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fetch_engine.state_nxt <= IFETCH_0;
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fetch_engine.state_nxt <= IFETCH_0;
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else -- uncompressed
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else -- compressed
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ipb.wdata <= ci_illegal & fetch_engine.i_buf(33 downto 32) & '1' & ci_instr32;
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ipb.wdata <= ci_illegal & fetch_engine.i_buf(33 downto 32) & '1' & ci_instr32;
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fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(2, data_width_c));
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fetch_engine.pc_fetch_add <= std_ulogic_vector(to_unsigned(2, data_width_c));
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fetch_engine.pc_real_add <= std_ulogic_vector(to_unsigned(2, data_width_c));
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fetch_engine.pc_real_add <= std_ulogic_vector(to_unsigned(2, data_width_c));
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fetch_engine.state_nxt <= IFETCH_0;
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fetch_engine.state_nxt <= IFETCH_0;
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end if;
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end if;
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Line 527... |
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-- for registers that do NOT require a specific reset state --
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-- for registers that do NOT require a specific reset state --
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execute_engine_fsm_sync: process(clk_i)
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execute_engine_fsm_sync: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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execute_engine.state_prev <= execute_engine.state;
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execute_engine.i_reg <= execute_engine.i_reg_nxt;
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execute_engine.i_reg <= execute_engine.i_reg_nxt;
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execute_engine.is_ci <= execute_engine.is_ci_nxt;
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execute_engine.is_ci <= execute_engine.is_ci_nxt;
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execute_engine.is_jump <= execute_engine.is_jump_nxt;
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execute_engine.is_jump <= execute_engine.is_jump_nxt;
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-- control signals --
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--
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ctrl <= ctrl_nxt;
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ctrl <= ctrl_nxt;
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end if;
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end if;
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end process execute_engine_fsm_sync;
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end process execute_engine_fsm_sync;
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-- PC output --
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-- PC output --
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Line 687... |
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= alu_immediate_v; -- use IMM as ALU.OPB for immediate operations
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ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= alu_immediate_v; -- use IMM as ALU.OPB for immediate operations
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ctrl_nxt(ctrl_alu_opc_mux_c) <= not alu_immediate_v;
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ctrl_nxt(ctrl_alu_opc_mux_c) <= not alu_immediate_v;
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ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_operation_v; -- actual ALU operation
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ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_operation_v; -- actual ALU operation
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ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "00"; -- RF input = ALU result
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ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "00"; -- RF input = ALU result
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-- multi cycle alu operation? --
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-- multi cycle alu operation? --
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if (alu_operation_v = alu_cmd_shift_c) or -- shift operation
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if (alu_operation_v = alu_cmd_shift_c) or -- shift operation?
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((CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_alu_c) and
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((CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_alu_c) and
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(execute_engine.i_reg(instr_funct7_lsb_c) = '1')) then -- MULDIV?
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(execute_engine.i_reg(instr_funct7_lsb_c) = '1')) then -- MULDIV?
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execute_engine.state_nxt <= ALU_WAIT;
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execute_engine.state_nxt <= ALU_WAIT;
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else
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else
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ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
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ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
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| Line 699... |
Line 701... |
if (CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_alu_c) and
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if (CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_alu_c) and
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(execute_engine.i_reg(instr_funct7_lsb_c) = '1') then -- MULDIV?
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(execute_engine.i_reg(instr_funct7_lsb_c) = '1') then -- MULDIV?
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ctrl_nxt(ctrl_cp_use_c) <= '1'; -- use CP
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ctrl_nxt(ctrl_cp_use_c) <= '1'; -- use CP
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end if;
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end if;
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when opcode_lui_c | opcode_auipc_c => -- load upper immediate (add to PC)
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when opcode_lui_c | opcode_auipc_c => -- load upper immediate (add to PC)
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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ctrl_nxt(ctrl_rf_clear_rs1_c) <= '1'; -- force RS1 = r0 (only relevant for LUI)
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ctrl_nxt(ctrl_rf_clear_rs1_c) <= '1'; -- force RS1 = r0 (only relevant for LUI)
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if (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_auipc_c) then -- AUIPC
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if (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_auipc_c) then -- AUIPC
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ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '1'; -- use PC as ALU.OPA
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ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '1'; -- use PC as ALU.OPA
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| Line 837... |
Line 838... |
-- RF write back --
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-- RF write back --
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ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "11"; -- RF input = CSR output
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ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "11"; -- RF input = CSR output
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ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
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ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
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execute_engine.state_nxt <= DISPATCH; -- FIXME should be SYS_WAIT? have another cycle to let side-effects kick in
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execute_engine.state_nxt <= DISPATCH; -- FIXME should be SYS_WAIT? have another cycle to let side-effects kick in
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when ALU_WAIT => -- wait for multi-cycle ALU operation to finish
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when ALU_WAIT => -- wait for multi-cycle ALU operation (shifter or CP) to finish
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_operation_v; -- actual ALU operation
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ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_shift_c;
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ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "00"; -- RF input = ALU result
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ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "00"; -- RF input = ALU result
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ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back (permanent write-back)
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ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back (permanent write-back)
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-- cp access? --
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if (CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_funct7_lsb_c) = '1') then -- MULDIV?
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ctrl_nxt(ctrl_cp_use_c) <= '1'; -- use CP
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end if;
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-- wait for result --
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if (alu_wait_i = '0') then
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if (alu_wait_i = '0') then
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execute_engine.state_nxt <= DISPATCH;
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execute_engine.state_nxt <= DISPATCH;
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end if;
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end if;
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when BRANCH => -- update PC for taken branches and jumps
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when BRANCH => -- update PC for taken branches and jumps
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Line 1624... |
when x"c82" | x"b82" => -- R/(W): instreth/minstreth: Instructions-retired counter HIGH
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when x"c82" | x"b82" => -- R/(W): instreth/minstreth: Instructions-retired counter HIGH
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csr_rdata_o <= x"000" & csr.minstreth(19 downto 0); -- only the lowest 20 bit!
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csr_rdata_o <= x"000" & csr.minstreth(19 downto 0); -- only the lowest 20 bit!
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-- machine information registers --
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-- machine information registers --
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when x"f11" => -- R/-: mvendorid
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when x"f11" => -- R/-: mvendorid
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csr_rdata_o <= (others => '0'); -- not yet assigned for NEORV32
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csr_rdata_o <= (others => '0'); -- not available for NEORV32
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when x"f12" => -- R/-: marchid
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when x"f12" => -- R/-: marchid
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csr_rdata_o <= (others => '0'); -- not yet assigned for NEORV32
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csr_rdata_o <= (others => '0'); -- not available for NEORV32
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when x"f13" => -- R/-: mimpid - implementation ID / NEORV32: version
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when x"f13" => -- R/-: mimpid - implementation ID / NEORV32: version
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csr_rdata_o <= hw_version_c;
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csr_rdata_o <= hw_version_c;
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when x"f14" => -- R/-: mhartid - hardware thread ID
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when x"f14" => -- R/-: mhartid - hardware thread ID
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csr_rdata_o <= HW_THREAD_ID;
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csr_rdata_o <= HW_THREAD_ID;
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| Line 1692... |
Line 1698... |
-- minstret (instret) --
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-- minstret (instret) --
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minstret_msb <= csr.minstret(csr.minstret'left);
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minstret_msb <= csr.minstret(csr.minstret'left);
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if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b02") then -- write access
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if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b02") then -- write access
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csr.minstret(31 downto 0) <= csr_wdata_i;
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csr.minstret(31 downto 0) <= csr_wdata_i;
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csr.minstret(32) <= '0';
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csr.minstret(32) <= '0';
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elsif (execute_engine.state_nxt /= EXECUTE) and (execute_engine.state = EXECUTE) then -- automatic update
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elsif (execute_engine.state_prev /= EXECUTE) and (execute_engine.state = EXECUTE) then -- automatic update
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csr.minstret <= std_ulogic_vector(unsigned(csr.minstret) + 1);
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csr.minstret <= std_ulogic_vector(unsigned(csr.minstret) + 1);
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end if;
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end if;
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-- minstreth (instreth) --
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-- minstreth (instreth) --
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if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b82") then -- write access
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if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b82") then -- write access
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