| Line 44... |
Line 44... |
use neorv32.neorv32_package.all;
|
use neorv32.neorv32_package.all;
|
|
|
entity neorv32_cpu_control is
|
entity neorv32_cpu_control is
|
generic (
|
generic (
|
-- General --
|
-- General --
|
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
|
|
HW_THREAD_ID : std_ulogic_vector(31 downto 0):= x"00000000"; -- hardware thread id
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HW_THREAD_ID : std_ulogic_vector(31 downto 0):= x"00000000"; -- hardware thread id
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CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
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CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
| Line 237... |
Line 236... |
end record;
|
end record;
|
signal csr : csr_t;
|
signal csr : csr_t;
|
|
|
signal mcycle_msb : std_ulogic;
|
signal mcycle_msb : std_ulogic;
|
signal minstret_msb : std_ulogic;
|
signal minstret_msb : std_ulogic;
|
signal systime : std_ulogic_vector(63 downto 0);
|
|
|
|
-- illegal instruction check --
|
-- illegal instruction check --
|
signal illegal_instruction : std_ulogic;
|
signal illegal_instruction : std_ulogic;
|
signal illegal_register : std_ulogic; -- only for E-extension
|
signal illegal_register : std_ulogic; -- only for E-extension
|
signal illegal_compressed : std_ulogic; -- only fir C-extension
|
signal illegal_compressed : std_ulogic; -- only fir C-extension
|
| Line 253... |
Line 251... |
|
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
-- Instruction Fetch
|
-- Instruction Fetch
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
|
|
-- Compressed Instructions Recoding -------------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
neorv32_cpu_decompressor_inst_true:
|
|
if (CPU_EXTENSION_RISCV_C = true) generate
|
|
neorv32_cpu_decompressor_inst: neorv32_cpu_decompressor
|
|
port map (
|
|
-- instruction input --
|
|
ci_instr16_i => fetch_engine.ci_input, -- compressed instruction input
|
|
-- instruction output --
|
|
ci_illegal_o => ci_illegal, -- is an illegal compressed instruction
|
|
ci_instr32_o => ci_instr32 -- 32-bit decompressed instruction
|
|
);
|
|
end generate;
|
|
|
|
neorv32_cpu_decompressor_inst_false:
|
|
if (CPU_EXTENSION_RISCV_C = false) generate
|
|
ci_instr32 <= (others => '0');
|
|
ci_illegal <= '0';
|
|
end generate;
|
|
|
|
|
|
-- Fetch Engine FSM Sync ------------------------------------------------------------------
|
-- Fetch Engine FSM Sync ------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- for registers that require a specific reset state --
|
-- registers that require a specific reset state --
|
fetch_engine_fsm_sync_rst: process(rstn_i, clk_i)
|
fetch_engine_fsm_sync_rst: process(rstn_i, clk_i)
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
fetch_engine.state <= IFETCH_RESET;
|
fetch_engine.state <= IFETCH_RESET;
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
| Line 291... |
Line 268... |
end if;
|
end if;
|
end if;
|
end if;
|
end process fetch_engine_fsm_sync_rst;
|
end process fetch_engine_fsm_sync_rst;
|
|
|
|
|
-- for registers that DO NOT require a specific reset state --
|
-- registers that DO NOT require a specific reset state --
|
fetch_engine_fsm_sync: process(clk_i)
|
fetch_engine_fsm_sync: process(clk_i)
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
if (fetch_engine.state = IFETCH_RESET) then
|
if (fetch_engine.state = IFETCH_RESET) then
|
fetch_engine.pc <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- initialize with "real" application PC
|
fetch_engine.pc <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- initialize with "real" application PC
|
| Line 402... |
Line 379... |
|
|
end case;
|
end case;
|
end process fetch_engine_fsm_comb;
|
end process fetch_engine_fsm_comb;
|
|
|
|
|
|
-- Compressed Instructions Recoding -------------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
neorv32_cpu_decompressor_inst_true:
|
|
if (CPU_EXTENSION_RISCV_C = true) generate
|
|
neorv32_cpu_decompressor_inst: neorv32_cpu_decompressor
|
|
port map (
|
|
-- instruction input --
|
|
ci_instr16_i => fetch_engine.ci_input, -- compressed instruction input
|
|
-- instruction output --
|
|
ci_illegal_o => ci_illegal, -- is an illegal compressed instruction
|
|
ci_instr32_o => ci_instr32 -- 32-bit decompressed instruction
|
|
);
|
|
end generate;
|
|
|
|
neorv32_cpu_decompressor_inst_false:
|
|
if (CPU_EXTENSION_RISCV_C = false) generate
|
|
ci_instr32 <= (others => '0');
|
|
ci_illegal <= '0';
|
|
end generate;
|
|
|
|
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
-- Instruction Prefetch Buffer
|
-- Instruction Prefetch Buffer
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
|
|
|
|
| Line 525... |
Line 523... |
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
execute_engine.pc <= CPU_BOOT_ADDR(data_width_c-1 downto 1) & '0';
|
execute_engine.pc <= CPU_BOOT_ADDR(data_width_c-1 downto 1) & '0';
|
execute_engine.last_pc <= CPU_BOOT_ADDR(data_width_c-1 downto 1) & '0';
|
execute_engine.last_pc <= CPU_BOOT_ADDR(data_width_c-1 downto 1) & '0';
|
execute_engine.state <= SYS_WAIT;
|
execute_engine.state <= SYS_WAIT;
|
execute_engine.sleep <= '0';
|
execute_engine.sleep <= '0';
|
execute_engine.if_rst <= '1'; -- IF is reset after system reset
|
execute_engine.if_rst <= '1'; -- instruction fetch is reset after system reset
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
execute_engine.pc <= execute_engine.pc_nxt(data_width_c-1 downto 1) & '0';
|
execute_engine.pc <= execute_engine.pc_nxt(data_width_c-1 downto 1) & '0';
|
if (execute_engine.state = EXECUTE) then
|
if (execute_engine.state = EXECUTE) then
|
execute_engine.last_pc <= execute_engine.pc(data_width_c-1 downto 1) & '0';
|
execute_engine.last_pc <= execute_engine.pc(data_width_c-1 downto 1) & '0';
|
end if;
|
end if;
|
| Line 710... |
Line 708... |
ctrl_nxt(ctrl_alu_opc_mux_c) <= not alu_immediate_v;
|
ctrl_nxt(ctrl_alu_opc_mux_c) <= not alu_immediate_v;
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_operation_v; -- actual ALU operation
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_operation_v; -- actual ALU operation
|
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "00"; -- RF input = ALU result
|
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "00"; -- RF input = ALU result
|
-- multi cycle alu operation? --
|
-- multi cycle alu operation? --
|
if (alu_operation_v = alu_cmd_shift_c) or -- shift operation?
|
if (alu_operation_v = alu_cmd_shift_c) or -- shift operation?
|
((CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_alu_c) and
|
((CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and
|
(execute_engine.i_reg(instr_funct7_lsb_c) = '1')) then -- MULDIV?
|
(execute_engine.i_reg(instr_funct7_lsb_c) = '1')) then -- MULDIV?
|
execute_engine.state_nxt <= ALU_WAIT;
|
execute_engine.state_nxt <= ALU_WAIT;
|
else
|
else
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
|
execute_engine.state_nxt <= DISPATCH;
|
execute_engine.state_nxt <= DISPATCH;
|
end if;
|
end if;
|
-- cp access? --
|
-- cp access? --
|
if (CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_alu_c) and
|
if (CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and
|
(execute_engine.i_reg(instr_funct7_lsb_c) = '1') then -- MULDIV?
|
(execute_engine.i_reg(instr_funct7_lsb_c) = '1') then -- MULDIV?
|
ctrl_nxt(ctrl_cp_use_c) <= '1'; -- use CP
|
ctrl_nxt(ctrl_cp_use_c) <= '1'; -- use CP
|
end if;
|
end if;
|
|
|
when opcode_lui_c | opcode_auipc_c => -- load upper immediate (add to PC)
|
when opcode_lui_c | opcode_auipc_c => -- load upper immediate (add to PC)
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
ctrl_nxt(ctrl_rf_clear_rs1_c) <= '1'; -- force RS1 = r0 (only relevant for LUI)
|
ctrl_nxt(ctrl_rf_clear_rs1_c) <= '1'; -- force RS1 = r0 (only relevant for LUI)
|
if (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_auipc_c) then -- AUIPC
|
if (execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_auipc_c(5)) then -- AUIPC
|
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '1'; -- use PC as ALU.OPA
|
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '1'; -- use PC as ALU.OPA
|
else -- LUI
|
else -- LUI
|
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '0'; -- use RS1 as ALU.OPA
|
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '0'; -- use RS1 as ALU.OPA
|
end if;
|
end if;
|
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '1'; -- use IMM as ALU.OPB
|
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '1'; -- use IMM as ALU.OPB
|
| Line 756... |
Line 754... |
execute_engine.state_nxt <= BRANCH;
|
execute_engine.state_nxt <= BRANCH;
|
|
|
when opcode_jal_c | opcode_jalr_c => -- jump and link (with register)
|
when opcode_jal_c | opcode_jalr_c => -- jump and link (with register)
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
-- compute target address --
|
-- compute target address --
|
if (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_jal_c) then -- JAL
|
if (execute_engine.i_reg(instr_opcode_lsb_c+3) = opcode_jal_c(3)) then -- JAL
|
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '1'; -- use PC as ALU.OPA
|
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '1'; -- use PC as ALU.OPA
|
else -- JALR
|
else -- JALR
|
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '0'; -- use RS1 as ALU.OPA
|
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '0'; -- use RS1 as ALU.OPA
|
end if;
|
end if;
|
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '1'; -- use IMM as ALU.OPB
|
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '1'; -- use IMM as ALU.OPB
|
| Line 771... |
Line 769... |
execute_engine.is_jump_nxt <= '1'; -- this is a jump operation
|
execute_engine.is_jump_nxt <= '1'; -- this is a jump operation
|
execute_engine.state_nxt <= BRANCH;
|
execute_engine.state_nxt <= BRANCH;
|
|
|
when opcode_fence_c => -- fence operations
|
when opcode_fence_c => -- fence operations
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fencei_c) and (CPU_EXTENSION_RISCV_Zifencei = true) then -- FENCE.I
|
if (execute_engine.i_reg(instr_funct3_lsb_c) = funct3_fencei_c(0)) and (CPU_EXTENSION_RISCV_Zifencei = true) then -- FENCE.I
|
fetch_engine.reset <= '1';
|
fetch_engine.reset <= '1';
|
execute_engine.if_rst_nxt <= '1'; -- this is a non-linear PC modification
|
execute_engine.if_rst_nxt <= '1'; -- this is a non-linear PC modification
|
execute_engine.pc_nxt <= execute_engine.next_pc; -- "refetch" next instruction (only relevant for fence.i)
|
execute_engine.pc_nxt <= execute_engine.next_pc; -- "refetch" next instruction (only relevant for fence.i)
|
ctrl_nxt(ctrl_bus_fencei_c) <= '1';
|
ctrl_nxt(ctrl_bus_fencei_c) <= '1';
|
end if;
|
end if;
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fence_c) then -- FENCE
|
if (execute_engine.i_reg(instr_funct3_lsb_c) = funct3_fence_c(0)) then -- FENCE
|
ctrl_nxt(ctrl_bus_fence_c) <= '1';
|
ctrl_nxt(ctrl_bus_fence_c) <= '1';
|
end if;
|
end if;
|
execute_engine.state_nxt <= SYS_WAIT;
|
execute_engine.state_nxt <= SYS_WAIT;
|
|
|
when opcode_syscsr_c => -- system/csr access
|
when opcode_syscsr_c => -- system/csr access
|
| Line 819... |
Line 817... |
ctrl_nxt(ctrl_alu_opa_mux_msb_c) <= '0'; -- default
|
ctrl_nxt(ctrl_alu_opa_mux_msb_c) <= '0'; -- default
|
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '0'; -- default
|
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '0'; -- default
|
ctrl_nxt(ctrl_alu_opb_mux_msb_c) <= '0'; -- default
|
ctrl_nxt(ctrl_alu_opb_mux_msb_c) <= '0'; -- default
|
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '0'; -- default
|
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '0'; -- default
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_or_c; -- default ALU operation = OR
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_or_c; -- default ALU operation = OR
|
|
-- ctrl_nxt(ctrl_alu_bmop2_c downto ctrl_alu_bmop0_c) <= alu_bm_andn_c; -- bit manipulation operation = ANDN
|
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is
|
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is
|
-- register operations --
|
-- register operations --
|
when funct3_csrrw_c => -- CSRRW
|
when funct3_csrrw_c => -- CSRRW
|
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '0'; -- OPA = rs1
|
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '0'; -- OPA = rs1
|
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '0'; -- OPB = rs2
|
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '0'; -- OPB = rs2
|
| Line 835... |
Line 834... |
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_or_c; -- actual ALU operation = OR
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_or_c; -- actual ALU operation = OR
|
csr.we_nxt <= (not rs1_is_r0_v) and csr_acc_valid; -- write CSR if rs1 is not zero_reg and if valid access
|
csr.we_nxt <= (not rs1_is_r0_v) and csr_acc_valid; -- write CSR if rs1 is not zero_reg and if valid access
|
when funct3_csrrc_c => -- CSRRC
|
when funct3_csrrc_c => -- CSRRC
|
ctrl_nxt(ctrl_alu_opa_mux_msb_c) <= '1'; -- OPA = csr
|
ctrl_nxt(ctrl_alu_opa_mux_msb_c) <= '1'; -- OPA = csr
|
ctrl_nxt(ctrl_alu_opb_mux_msb_c) <= '1'; -- OPB = rs1
|
ctrl_nxt(ctrl_alu_opb_mux_msb_c) <= '1'; -- OPB = rs1
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_bitc_c; -- actual ALU operation = bit clear
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_bitm_c; -- actual ALU operation = bit manipulation (ANDN)
|
csr.we_nxt <= (not rs1_is_r0_v) and csr_acc_valid; -- write CSR if rs1 is not zero_reg and if valid access
|
csr.we_nxt <= (not rs1_is_r0_v) and csr_acc_valid; -- write CSR if rs1 is not zero_reg and if valid access
|
-- immediate operations --
|
-- immediate operations --
|
when funct3_csrrwi_c => -- CSRRWI
|
when funct3_csrrwi_c => -- CSRRWI
|
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '0'; -- OPA = rs1
|
ctrl_nxt(ctrl_alu_opa_mux_lsb_c) <= '0'; -- OPA = rs1
|
ctrl_nxt(ctrl_rf_clear_rs1_c) <= '1'; -- rs1 = 0
|
ctrl_nxt(ctrl_rf_clear_rs1_c) <= '1'; -- rs1 = 0
|
| Line 852... |
Line 851... |
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_or_c; -- actual ALU operation = OR
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_or_c; -- actual ALU operation = OR
|
csr.we_nxt <= (not rs1_is_r0_v) and csr_acc_valid; -- write CSR if UIMM5 is not zero (bits from rs1 filed) and if valid access
|
csr.we_nxt <= (not rs1_is_r0_v) and csr_acc_valid; -- write CSR if UIMM5 is not zero (bits from rs1 filed) and if valid access
|
when funct3_csrrci_c => -- CSRRCI
|
when funct3_csrrci_c => -- CSRRCI
|
ctrl_nxt(ctrl_alu_opa_mux_msb_c) <= '1'; -- OPA = csr
|
ctrl_nxt(ctrl_alu_opa_mux_msb_c) <= '1'; -- OPA = csr
|
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '1'; -- OPB = immediate
|
ctrl_nxt(ctrl_alu_opb_mux_lsb_c) <= '1'; -- OPB = immediate
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_bitc_c; -- actual ALU operation = bit clear
|
ctrl_nxt(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) <= alu_cmd_bitm_c; -- actual ALU operation = bit manipulation (ANDN)
|
csr.we_nxt <= (not rs1_is_r0_v) and csr_acc_valid; -- write CSR if UIMM5 is not zero (bits from rs1 filed) and if valid access
|
csr.we_nxt <= (not rs1_is_r0_v) and csr_acc_valid; -- write CSR if UIMM5 is not zero (bits from rs1 filed) and if valid access
|
when others => -- undefined
|
when others => -- undefined
|
NULL;
|
NULL;
|
end case;
|
end case;
|
-- RF write back --
|
-- RF write back --
|
| Line 908... |
Line 907... |
ctrl_nxt(ctrl_bus_mdi_we_c) <= '1'; -- keep writing input data to MDI (only relevant for LOAD)
|
ctrl_nxt(ctrl_bus_mdi_we_c) <= '1'; -- keep writing input data to MDI (only relevant for LOAD)
|
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "01"; -- RF input = memory input (only relevant for LOAD)
|
ctrl_nxt(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) <= "01"; -- RF input = memory input (only relevant for LOAD)
|
if (ma_load_i = '1') or (be_load_i = '1') or (ma_store_i = '1') or (be_store_i = '1') then -- abort if exception
|
if (ma_load_i = '1') or (be_load_i = '1') or (ma_store_i = '1') or (be_store_i = '1') then -- abort if exception
|
execute_engine.state_nxt <= SYS_WAIT;
|
execute_engine.state_nxt <= SYS_WAIT;
|
elsif (bus_d_wait_i = '0') then -- wait here for bus to finish transaction
|
elsif (bus_d_wait_i = '0') then -- wait here for bus to finish transaction
|
if (execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) = opcode_load_c) then -- LOAD?
|
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') then -- LOAD
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
|
end if;
|
end if;
|
execute_engine.state_nxt <= DISPATCH;
|
execute_engine.state_nxt <= DISPATCH;
|
end if;
|
end if;
|
|
|
| Line 939... |
Line 938... |
if (csr.privilege = m_priv_mode_c) then
|
if (csr.privilege = m_priv_mode_c) then
|
is_m_mode_v := '1';
|
is_m_mode_v := '1';
|
end if;
|
end if;
|
|
|
-- check CSR access --
|
-- check CSR access --
|
csr_acc_valid <= '0'; -- default
|
|
case execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) is
|
case execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) is
|
when x"300" => csr_acc_valid <= is_m_mode_v; -- mstatus
|
when x"300" => csr_acc_valid <= is_m_mode_v; -- mstatus
|
when x"301" => csr_acc_valid <= is_m_mode_v; -- misa
|
when x"301" => csr_acc_valid <= is_m_mode_v; -- misa
|
when x"304" => csr_acc_valid <= is_m_mode_v; -- mie
|
when x"304" => csr_acc_valid <= is_m_mode_v; -- mie
|
when x"305" => csr_acc_valid <= is_m_mode_v; -- mtvev
|
when x"305" => csr_acc_valid <= is_m_mode_v; -- mtvev
|
| Line 963... |
Line 961... |
when x"3b4" => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 5)) and is_m_mode_v; -- pmpaddr4
|
when x"3b4" => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 5)) and is_m_mode_v; -- pmpaddr4
|
when x"3b5" => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 6)) and is_m_mode_v; -- pmpaddr5
|
when x"3b5" => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 6)) and is_m_mode_v; -- pmpaddr5
|
when x"3b6" => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 7)) and is_m_mode_v; -- pmpaddr6
|
when x"3b6" => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 7)) and is_m_mode_v; -- pmpaddr6
|
when x"3b7" => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 8)) and is_m_mode_v; -- pmpaddr7
|
when x"3b7" => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 8)) and is_m_mode_v; -- pmpaddr7
|
--
|
--
|
when x"c00" => csr_acc_valid <= bool_to_ulogic_f(CSR_COUNTERS_USE); -- cycle
|
when x"c00" => csr_acc_valid <= '1'; -- cycle
|
when x"c01" => csr_acc_valid <= bool_to_ulogic_f(CSR_COUNTERS_USE); -- time
|
when x"c01" => csr_acc_valid <= '1'; -- time
|
when x"c02" => csr_acc_valid <= bool_to_ulogic_f(CSR_COUNTERS_USE); -- instret
|
when x"c02" => csr_acc_valid <= '1'; -- instret
|
when x"c80" => csr_acc_valid <= bool_to_ulogic_f(CSR_COUNTERS_USE); -- cycleh
|
when x"c80" => csr_acc_valid <= '1'; -- cycleh
|
when x"c81" => csr_acc_valid <= bool_to_ulogic_f(CSR_COUNTERS_USE); -- timeh
|
when x"c81" => csr_acc_valid <= '1'; -- timeh
|
when x"c82" => csr_acc_valid <= bool_to_ulogic_f(CSR_COUNTERS_USE); -- instreth
|
when x"c82" => csr_acc_valid <= '1'; -- instreth
|
--
|
--
|
when x"b00" => csr_acc_valid <= bool_to_ulogic_f(CSR_COUNTERS_USE) and is_m_mode_v; -- mcycle
|
when x"b00" => csr_acc_valid <= is_m_mode_v; -- mcycle
|
when x"b02" => csr_acc_valid <= bool_to_ulogic_f(CSR_COUNTERS_USE) and is_m_mode_v; -- minstret
|
when x"b02" => csr_acc_valid <= is_m_mode_v; -- minstret
|
when x"b80" => csr_acc_valid <= bool_to_ulogic_f(CSR_COUNTERS_USE) and is_m_mode_v; -- mcycleh
|
when x"b80" => csr_acc_valid <= is_m_mode_v; -- mcycleh
|
when x"b82" => csr_acc_valid <= bool_to_ulogic_f(CSR_COUNTERS_USE) and is_m_mode_v; -- minstreth
|
when x"b82" => csr_acc_valid <= is_m_mode_v; -- minstreth
|
--
|
--
|
when x"f11" => csr_acc_valid <= is_m_mode_v; -- mvendorid
|
when x"f11" => csr_acc_valid <= is_m_mode_v; -- mvendorid
|
when x"f12" => csr_acc_valid <= is_m_mode_v; -- marchid
|
when x"f12" => csr_acc_valid <= is_m_mode_v; -- marchid
|
when x"f13" => csr_acc_valid <= is_m_mode_v; -- mimpid
|
when x"f13" => csr_acc_valid <= is_m_mode_v; -- mimpid
|
when x"f14" => csr_acc_valid <= is_m_mode_v; -- mhartid
|
when x"f14" => csr_acc_valid <= is_m_mode_v; -- mhartid
|
--
|
--
|
when x"fc0" => csr_acc_valid <= is_m_mode_v; -- mzext (custom CSR)
|
when x"fc0" => csr_acc_valid <= is_m_mode_v; -- mzext (custom CSR)
|
--
|
--
|
when others => csr_acc_valid <= '0'; -- undefined
|
when others => csr_acc_valid <= '0'; -- undefined, invalid access
|
end case;
|
end case;
|
end process invalid_csr_access_check;
|
end process invalid_csr_access_check;
|
|
|
|
|
-- Illegal Instruction Check --------------------------------------------------------------
|
-- Illegal Instruction Check --------------------------------------------------------------
|
| Line 998... |
Line 996... |
if (execute_engine.state = EXECUTE) then
|
if (execute_engine.state = EXECUTE) then
|
-- defaults --
|
-- defaults --
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
illegal_register <= '0';
|
illegal_register <= '0';
|
|
|
-- check if using reg >= 16 for E-CPUs --
|
|
--if (CPU_EXTENSION_RISCV_E = true) then
|
|
-- illegal_register <= ????? FIXME
|
|
--else
|
|
-- illegal_register <= '0';
|
|
--end if;
|
|
|
|
-- check instructions --
|
-- check instructions --
|
case execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) is
|
case execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c) is
|
|
|
-- OPCODE check sufficient: LUI, UIPC, JAL --
|
-- OPCODE check sufficient: LUI, UIPC, JAL --
|
when opcode_lui_c | opcode_auipc_c | opcode_jal_c =>
|
when opcode_lui_c | opcode_auipc_c | opcode_jal_c =>
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
|
-- illegal E-CPU register? --
|
|
if (CPU_EXTENSION_RISCV_E = true) and (execute_engine.i_reg(instr_rd_msb_c) = '1') then
|
|
illegal_register <= '1';
|
|
end if;
|
|
|
when opcode_alui_c => -- check ALUI funct7
|
when opcode_alui_c => -- check ALUI funct7
|
if ((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) and
|
if ((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) and
|
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0000000")) or -- shift logical left
|
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0000000")) or -- shift logical left
|
((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c) and
|
((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c) and
|
| Line 1022... |
Line 1017... |
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0100000"))) then -- shift right
|
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0100000"))) then -- shift right
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
else
|
else
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
end if;
|
end if;
|
|
-- illegal E-CPU register? --
|
|
if (CPU_EXTENSION_RISCV_E = true) and ((execute_engine.i_reg(instr_rs1_msb_c) = '1') or (execute_engine.i_reg(instr_rd_msb_c) = '1')) then
|
|
illegal_register <= '1';
|
|
end if;
|
|
|
when opcode_load_c => -- check LOAD funct3
|
when opcode_load_c => -- check LOAD funct3
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lb_c) or
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lb_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lh_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lh_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lw_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lw_c) or
|
| Line 1033... |
Line 1032... |
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lhu_c) then
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lhu_c) then
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
else
|
else
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
end if;
|
end if;
|
|
-- illegal E-CPU register? --
|
|
if (CPU_EXTENSION_RISCV_E = true) and ((execute_engine.i_reg(instr_rs1_msb_c) = '1') or (execute_engine.i_reg(instr_rd_msb_c) = '1')) then
|
|
illegal_register <= '1';
|
|
end if;
|
|
|
when opcode_store_c => -- check STORE funct3
|
when opcode_store_c => -- check STORE funct3
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sb_c) or
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sb_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sh_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sh_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sw_c) then
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sw_c) then
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
else
|
else
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
end if;
|
end if;
|
|
-- illegal E-CPU register? --
|
|
if (CPU_EXTENSION_RISCV_E = true) and ((execute_engine.i_reg(instr_rs2_msb_c) = '1') or (execute_engine.i_reg(instr_rs1_msb_c) = '1')) then
|
|
illegal_register <= '1';
|
|
end if;
|
|
|
when opcode_branch_c => -- check BRANCH funct3
|
when opcode_branch_c => -- check BRANCH funct3
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_beq_c) or
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_beq_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bne_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bne_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_blt_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_blt_c) or
|
| Line 1054... |
Line 1061... |
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bgeu_c) then
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_bgeu_c) then
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
else
|
else
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
end if;
|
end if;
|
|
-- illegal E-CPU register? --
|
|
if (CPU_EXTENSION_RISCV_E = true) and ((execute_engine.i_reg(instr_rs2_msb_c) = '1') or (execute_engine.i_reg(instr_rs1_msb_c) = '1')) then
|
|
illegal_register <= '1';
|
|
end if;
|
|
|
when opcode_jalr_c => -- check JALR funct3
|
when opcode_jalr_c => -- check JALR funct3
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "000") then
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "000") then
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
else
|
else
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
end if;
|
end if;
|
|
-- illegal E-CPU register? --
|
|
if (CPU_EXTENSION_RISCV_E = true) and ((execute_engine.i_reg(instr_rs1_msb_c) = '1') or (execute_engine.i_reg(instr_rd_msb_c) = '1')) then
|
|
illegal_register <= '1';
|
|
end if;
|
|
|
when opcode_alu_c => -- check ALU funct3 & funct7
|
when opcode_alu_c => -- check ALU funct3 & funct7
|
if (execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000001") then -- MULDIV
|
if (execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000001") then -- MULDIV
|
if (CPU_EXTENSION_RISCV_M = false) then -- not implemented
|
if (CPU_EXTENSION_RISCV_M = false) then -- not implemented
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
| Line 1075... |
Line 1090... |
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0100000")) then -- ADD/SUB or SRA/SRL select
|
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) /= "0100000")) then -- ADD/SUB or SRA/SRL select
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
else
|
else
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
end if;
|
end if;
|
|
-- illegal E-CPU register? --
|
|
if (CPU_EXTENSION_RISCV_E = true) and
|
|
((execute_engine.i_reg(instr_rs2_msb_c) = '1') or (execute_engine.i_reg(instr_rs1_msb_c) = '1') or (execute_engine.i_reg(instr_rd_msb_c) = '1')) then
|
|
illegal_register <= '1';
|
|
end if;
|
|
|
when opcode_fence_c => -- fence instructions --
|
when opcode_fence_c => -- fence instructions --
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fencei_c) and (CPU_EXTENSION_RISCV_Zifencei = true) then -- FENCE.I
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fencei_c) and (CPU_EXTENSION_RISCV_Zifencei = true) then -- FENCE.I
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
elsif (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fence_c) then -- FENCE
|
elsif (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fence_c) then -- FENCE
|
| Line 1099... |
Line 1119... |
if (csr_acc_valid = '1') then
|
if (csr_acc_valid = '1') then
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
else
|
else
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
end if;
|
end if;
|
|
-- illegal E-CPU register? --
|
|
if (CPU_EXTENSION_RISCV_E = true) then
|
|
if (execute_engine.i_reg(instr_funct3_msb_c) = '0') then -- reg-reg CSR
|
|
illegal_register <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c);
|
|
else -- reg-imm CSR
|
|
illegal_register <= execute_engine.i_reg(instr_rd_msb_c);
|
|
end if;
|
|
end if;
|
|
|
-- ecall, ebreak, mret, wfi --
|
-- ecall, ebreak, mret, wfi --
|
elsif (execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c) = "00000") and
|
elsif (execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c) = "00000") and
|
(execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c) = "00000") then
|
(execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c) = "00000") then
|
if (execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_ecall_c) or -- ECALL
|
if (execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_ecall_c) or -- ECALL
|
| Line 1179... |
Line 1207... |
((execute_engine.state = EXECUTE) or (execute_engine.state = TRAP))) then -- sample IRQs in EXECUTE or TRAP state only -> continue execution even if permanent IRQ
|
((execute_engine.state = EXECUTE) or (execute_engine.state = TRAP))) then -- sample IRQs in EXECUTE or TRAP state only -> continue execution even if permanent IRQ
|
trap_ctrl.cause <= trap_ctrl.cause_nxt; -- capture source ID for program (for mcause csr)
|
trap_ctrl.cause <= trap_ctrl.cause_nxt; -- capture source ID for program (for mcause csr)
|
trap_ctrl.exc_ack <= '1'; -- clear execption
|
trap_ctrl.exc_ack <= '1'; -- clear execption
|
trap_ctrl.irq_ack <= trap_ctrl.irq_ack_nxt; -- capture and clear with interrupt ACK mask
|
trap_ctrl.irq_ack <= trap_ctrl.irq_ack_nxt; -- capture and clear with interrupt ACK mask
|
trap_ctrl.env_start <= '1'; -- now execute engine can start trap handler
|
trap_ctrl.env_start <= '1'; -- now execute engine can start trap handler
|
|
-- assert false report "NEORV32.CPU TRAP: mcause=" & integer'image(to_integer(unsigned(trap_ctrl.cause_nxt))) severity note; -- for debugging
|
end if;
|
end if;
|
else -- trap waiting to get started
|
else -- trap waiting to get started
|
if (trap_ctrl.env_start_ack = '1') then -- start of trap handler acknowledged by execution engine
|
if (trap_ctrl.env_start_ack = '1') then -- start of trap handler acknowledged by execution engine
|
trap_ctrl.exc_ack <= '0';
|
trap_ctrl.exc_ack <= '0';
|
trap_ctrl.irq_ack <= (others => '0');
|
trap_ctrl.irq_ack <= (others => '0');
|
| Line 1639... |
Line 1668... |
|
|
-- counter and timers --
|
-- counter and timers --
|
when x"c00" | x"b00" => -- R/(W): cycle/mcycle: Cycle counter LOW
|
when x"c00" | x"b00" => -- R/(W): cycle/mcycle: Cycle counter LOW
|
csr_rdata_o <= csr.mcycle(31 downto 0);
|
csr_rdata_o <= csr.mcycle(31 downto 0);
|
when x"c01" => -- R/-: time: System time LOW (from MTIME unit)
|
when x"c01" => -- R/-: time: System time LOW (from MTIME unit)
|
csr_rdata_o <= systime(31 downto 0);
|
csr_rdata_o <= time_i(31 downto 0);
|
when x"c02" | x"b02" => -- R/(W): instret/minstret: Instructions-retired counter LOW
|
when x"c02" | x"b02" => -- R/(W): instret/minstret: Instructions-retired counter LOW
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csr_rdata_o <= csr.minstret(31 downto 0);
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csr_rdata_o <= csr.minstret(31 downto 0);
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when x"c80" | x"b80" => -- R/(W): cycleh/mcycleh: Cycle counter HIGH
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when x"c80" | x"b80" => -- R/(W): cycleh/mcycleh: Cycle counter HIGH
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csr_rdata_o <= x"000" & csr.mcycleh(19 downto 0); -- only the lowest 20 bit!
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csr_rdata_o <= x"000" & csr.mcycleh(19 downto 0); -- only the lowest 20 bit!
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when x"c81" => -- R/-: timeh: System time HIGH (from MTIME unit)
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when x"c81" => -- R/-: timeh: System time HIGH (from MTIME unit)
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csr_rdata_o <= systime(63 downto 32);
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csr_rdata_o <= time_i(63 downto 32);
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when x"c82" | x"b82" => -- R/(W): instreth/minstreth: Instructions-retired counter HIGH
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when x"c82" | x"b82" => -- R/(W): instreth/minstreth: Instructions-retired counter HIGH
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csr_rdata_o <= x"000" & csr.minstreth(19 downto 0); -- only the lowest 20 bit!
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csr_rdata_o <= x"000" & csr.minstreth(19 downto 0); -- only the lowest 20 bit!
|
|
|
-- machine information registers --
|
-- machine information registers --
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when x"f11" => -- R/-: mvendorid
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when x"f11" => -- R/-: mvendorid
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csr_rdata_o <= (others => '0'); -- not available for NEORV32
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csr_rdata_o <= (others => '0'); -- not assigned
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when x"f12" => -- R/-: marchid
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when x"f12" => -- R/-: marchid
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csr_rdata_o <= (others => '0'); -- not available for NEORV32
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csr_rdata_o <= (others => '0'); -- not assigned
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when x"f13" => -- R/-: mimpid - implementation ID / NEORV32: version
|
when x"f13" => -- R/-: mimpid - implementation ID / NEORV32 version
|
csr_rdata_o <= hw_version_c;
|
csr_rdata_o <= hw_version_c;
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when x"f14" => -- R/-: mhartid - hardware thread ID
|
when x"f14" => -- R/-: mhartid - hardware thread ID
|
csr_rdata_o <= HW_THREAD_ID;
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csr_rdata_o <= HW_THREAD_ID;
|
|
|
-- custom machine read-only CSRs --
|
-- custom machine read-only CSRs --
|
when x"fc0" => -- R/-: mzext
|
when x"fc0" => -- R/-: mzext
|
csr_rdata_o(0) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr); -- Zicsr CPU extension
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csr_rdata_o(0) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr); -- Zicsr CPU extension
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csr_rdata_o(1) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- Zifencei CPU extension
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csr_rdata_o(1) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- Zifencei CPU extension
|
csr_rdata_o(2) <= bool_to_ulogic_f(CSR_COUNTERS_USE); -- std (performance) counters enabled
|
|
|
|
-- undefined/unavailable --
|
-- undefined/unavailable --
|
when others =>
|
when others =>
|
csr_rdata_o <= (others => '0'); -- not implemented
|
csr_rdata_o <= (others => '0'); -- not implemented
|
|
|
| Line 1676... |
Line 1704... |
csr_rdata_o <= (others => '0');
|
csr_rdata_o <= (others => '0');
|
end if;
|
end if;
|
end if;
|
end if;
|
end process csr_read_access;
|
end process csr_read_access;
|
|
|
-- time[h] CSR --
|
|
systime <= time_i when (CSR_COUNTERS_USE = true) else (others => '0');
|
|
|
|
-- CPU's current privilege level --
|
-- CPU's current privilege level --
|
priv_mode_o <= csr.privilege;
|
priv_mode_o <= csr.privilege;
|
|
|
-- PMP output --
|
-- PMP output --
|
pmp_output: process(csr)
|
pmp_output: process(csr)
|
| Line 1708... |
Line 1733... |
csr.mcycleh <= (others => '0');
|
csr.mcycleh <= (others => '0');
|
csr.minstreth <= (others => '0');
|
csr.minstreth <= (others => '0');
|
mcycle_msb <= '0';
|
mcycle_msb <= '0';
|
minstret_msb <= '0';
|
minstret_msb <= '0';
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
if (CSR_COUNTERS_USE = true) then
|
|
|
|
-- mcycle (cycle) --
|
-- mcycle (cycle) --
|
mcycle_msb <= csr.mcycle(csr.mcycle'left);
|
mcycle_msb <= csr.mcycle(csr.mcycle'left);
|
if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b00") then -- write access
|
if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b00") then -- write access
|
csr.mcycle(31 downto 0) <= csr_wdata_i;
|
csr.mcycle(31 downto 0) <= csr_wdata_i;
|
csr.mcycle(32) <= '0';
|
csr.mcycle(32) <= '0';
|
elsif (execute_engine.sleep = '0') then -- automatic update
|
elsif (execute_engine.sleep = '0') then -- automatic update (if CPU is not in sleep mode)
|
csr.mcycle <= std_ulogic_vector(unsigned(csr.mcycle) + 1);
|
csr.mcycle <= std_ulogic_vector(unsigned(csr.mcycle) + 1);
|
end if;
|
end if;
|
|
|
-- mcycleh (cycleh) --
|
-- mcycleh (cycleh) --
|
if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b80") then -- write access
|
if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b80") then -- write access
|
csr.mcycleh <= csr_wdata_i(19 downto 0);
|
csr.mcycleh <= csr_wdata_i(csr.mcycleh'left downto 0);
|
elsif ((mcycle_msb xor csr.mcycle(csr.mcycle'left)) = '1') then -- automatic update
|
elsif ((mcycle_msb xor csr.mcycle(csr.mcycle'left)) = '1') then -- automatic update
|
csr.mcycleh <= std_ulogic_vector(unsigned(csr.mcycleh) + 1);
|
csr.mcycleh <= std_ulogic_vector(unsigned(csr.mcycleh) + 1);
|
end if;
|
end if;
|
|
|
-- minstret (instret) --
|
-- minstret (instret) --
|
| Line 1737... |
Line 1761... |
csr.minstret <= std_ulogic_vector(unsigned(csr.minstret) + 1);
|
csr.minstret <= std_ulogic_vector(unsigned(csr.minstret) + 1);
|
end if;
|
end if;
|
|
|
-- minstreth (instreth) --
|
-- minstreth (instreth) --
|
if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b82") then -- write access
|
if (csr.we = '1') and (execute_engine.i_reg(31 downto 20) = x"b82") then -- write access
|
csr.minstreth <= csr_wdata_i(19 downto 0);
|
csr.minstreth <= csr_wdata_i(csr.minstreth'left downto 0);
|
elsif ((minstret_msb xor csr.minstret(csr.minstret'left)) = '1') then -- automatic update
|
elsif ((minstret_msb xor csr.minstret(csr.minstret'left)) = '1') then -- automatic update
|
csr.minstreth <= std_ulogic_vector(unsigned(csr.minstreth) + 1);
|
csr.minstreth <= std_ulogic_vector(unsigned(csr.minstreth) + 1);
|
end if;
|
end if;
|
|
|
else -- if not implemented
|
|
csr.mcycle <= (others => '0');
|
|
csr.minstret <= (others => '0');
|
|
csr.mcycleh <= (others => '0');
|
|
csr.minstreth <= (others => '0');
|
|
mcycle_msb <= '0';
|
|
minstret_msb <= '0';
|
|
end if;
|
|
end if;
|
end if;
|
end process csr_counters;
|
end process csr_counters;
|
|
|
|
|
end neorv32_cpu_control_rtl;
|
end neorv32_cpu_control_rtl;
|
