| Line 317... |
Line 317... |
when IFETCH_RESET => -- reset engine, prefetch buffer, get appilcation PC
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when IFETCH_RESET => -- reset engine, prefetch buffer, get appilcation PC
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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fetch_engine.i_buf_state_nxt <= (others => '0');
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fetch_engine.i_buf_state_nxt <= (others => '0');
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ipb.clear <= '1'; -- clear instruction prefetch buffer
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ipb.clear <= '1'; -- clear instruction prefetch buffer
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fetch_engine.state_nxt <= IFETCH_0;
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fetch_engine.state_nxt <= IFETCH_0;
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fetch_engine.bus_err_ack <= '1'; -- acknowledge any instruction bus errors, the execute engine has to take care of them / terminate current transfer
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|
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when IFETCH_0 => -- output current PC to bus system, request 32-bit word
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when IFETCH_0 => -- output current PC to bus system, request 32-bit word
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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bus_fast_ir <= '1'; -- fast instruction fetch request
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bus_fast_ir <= '1'; -- fast instruction fetch request
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fetch_engine.state_nxt <= IFETCH_1;
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fetch_engine.state_nxt <= IFETCH_1;
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| Line 329... |
Line 330... |
-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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if (bus_i_wait_i = '0') or (be_instr_i = '1') or (ma_instr_i = '1') then -- wait for bus response
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if (bus_i_wait_i = '0') or (be_instr_i = '1') or (ma_instr_i = '1') then -- wait for bus response
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fetch_engine.i_buf_nxt <= be_instr_i & ma_instr_i & instr_i(31 downto 0); -- store data word and exception info
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fetch_engine.i_buf_nxt <= be_instr_i & ma_instr_i & instr_i(31 downto 0); -- store data word and exception info
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fetch_engine.i_buf2_nxt <= fetch_engine.i_buf;
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fetch_engine.i_buf2_nxt <= fetch_engine.i_buf;
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fetch_engine.i_buf_state_nxt <= fetch_engine.i_buf_state(0) & '1';
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fetch_engine.i_buf_state_nxt <= fetch_engine.i_buf_state(0) & '1';
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fetch_engine.bus_err_ack <= '1'; -- acknowledge any instruction bus errors, the execute engine has to take care of them
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if (fetch_engine.i_buf_state(0) = '1') then -- buffer filled?
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if (fetch_engine.i_buf_state(0) = '1') then -- buffer filled?
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fetch_engine.state_nxt <= IFETCH_2;
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fetch_engine.state_nxt <= IFETCH_2;
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else
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else
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fetch_engine.pc_add <= std_ulogic_vector(to_unsigned(4, data_width_c));
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fetch_engine.pc_add <= std_ulogic_vector(to_unsigned(4, data_width_c));
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fetch_engine.state_nxt <= IFETCH_0; -- get another instruction word
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fetch_engine.state_nxt <= IFETCH_0; -- get another instruction word
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end if;
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end if;
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end if;
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end if;
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when IFETCH_2 => -- construct instruction word and issue
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when IFETCH_2 => -- construct instruction word and issue
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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fetch_engine.bus_err_ack <= '1'; -- acknowledge any instruction bus errors, the execute engine has to take care of them / terminate current transfer
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if (fetch_engine.pc(1) = '0') or (CPU_EXTENSION_RISCV_C = false) then -- 32-bit aligned
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if (fetch_engine.pc(1) = '0') or (CPU_EXTENSION_RISCV_C = false) then -- 32-bit aligned
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fetch_engine.ci_input <= fetch_engine.i_buf2(15 downto 00);
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fetch_engine.ci_input <= fetch_engine.i_buf2(15 downto 00);
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if (ipb.free = '1') then -- free entry in buffer?
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if (ipb.free = '1') then -- free entry in buffer?
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ipb.we <= '1';
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ipb.we <= '1';
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