| Line 73... |
Line 73... |
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
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IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
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IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
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IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
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IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
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IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
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IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
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IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
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IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)?
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IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)?
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IO_TRNG_USE : boolean := true -- implement true random number generator (TRNG)?
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IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)?
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IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
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);
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);
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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rstn_i : in std_ulogic; -- global reset, low-active, async
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| Line 386... |
Line 387... |
when funct3_sltu_c => alu_operation_v := alu_cmd_slt_c; -- SLTU(I)
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when funct3_sltu_c => alu_operation_v := alu_cmd_slt_c; -- SLTU(I)
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when funct3_xor_c => alu_operation_v := alu_cmd_xor_c; -- XOR(I)
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when funct3_xor_c => alu_operation_v := alu_cmd_xor_c; -- XOR(I)
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when funct3_sr_c => alu_operation_v := alu_cmd_shift_c; -- SRL(I) / SRA(I)
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when funct3_sr_c => alu_operation_v := alu_cmd_shift_c; -- SRL(I) / SRA(I)
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when funct3_or_c => alu_operation_v := alu_cmd_or_c; -- OR(I)
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when funct3_or_c => alu_operation_v := alu_cmd_or_c; -- OR(I)
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when funct3_and_c => alu_operation_v := alu_cmd_and_c; -- AND(I)
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when funct3_and_c => alu_operation_v := alu_cmd_and_c; -- AND(I)
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when others => alu_operation_v := (others => '-'); -- undefined
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when others => alu_operation_v := (others => '0'); -- undefined
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end case;
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end case;
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|
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-- is rs1 = r0? --
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-- is rs1 = r0? --
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rs1_is_r0_v := '0';
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rs1_is_r0_v := '0';
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if (i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c) = "00000") then
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if (i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c) = "00000") then
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| Line 901... |
Line 902... |
if (rstn_i = '0') then
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if (rstn_i = '0') then
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exc_buf <= (others => '0');
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exc_buf <= (others => '0');
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irq_buf <= (others => '0');
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irq_buf <= (others => '0');
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exc_ack <= (others => '0');
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exc_ack <= (others => '0');
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irq_ack <= (others => '0');
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irq_ack <= (others => '0');
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exc_src <= (others => '-');
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exc_src <= (others => '0');
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exc_cpu_start <= '0';
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exc_cpu_start <= '0';
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exc_cause <= (others => '0');
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exc_cause <= (others => '0');
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mtinst <= (others => '-');
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mtinst <= (others => '0');
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elsif rising_edge(clk_i) then
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elsif rising_edge(clk_i) then
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if (CPU_EXTENSION_RISCV_Zicsr = true) then
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if (CPU_EXTENSION_RISCV_Zicsr = true) then
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-- exception buffer: misaligned load/store/instruction address
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-- exception buffer: misaligned load/store/instruction address
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exc_buf(exception_lalign_c) <= (exc_buf(exception_lalign_c) or ma_load_i) and (not exc_ack(exception_lalign_c));
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exc_buf(exception_lalign_c) <= (exc_buf(exception_lalign_c) or ma_load_i) and (not exc_ack(exception_lalign_c));
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exc_buf(exception_salign_c) <= (exc_buf(exception_salign_c) or ma_store_i) and (not exc_ack(exception_salign_c));
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exc_buf(exception_salign_c) <= (exc_buf(exception_salign_c) or ma_store_i) and (not exc_ack(exception_salign_c));
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| Line 1090... |
Line 1091... |
mstatus_mie <= '0';
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mstatus_mie <= '0';
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mstatus_mpie <= '0';
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mstatus_mpie <= '0';
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mie_msie <= '0';
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mie_msie <= '0';
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mie_meie <= '0';
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mie_meie <= '0';
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mie_mtie <= '0';
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mie_mtie <= '0';
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mtvec <= (others => '-');
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mtvec <= (others => '0');
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mtval <= (others => '-');
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mtval <= (others => '0');
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mepc <= (others => '-');
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mepc <= (others => '0');
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mip_msip <= '-';
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mip_msip <= '0';
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elsif rising_edge(clk_i) then
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elsif rising_edge(clk_i) then
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if (CPU_EXTENSION_RISCV_Zicsr = true) then
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if (CPU_EXTENSION_RISCV_Zicsr = true) then
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mip_msip <= '0';
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mip_msip <= '0';
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-- register that can be modified by user --
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-- register that can be modified by user --
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if (ctrl(ctrl_csr_we_c) = '1') then -- manual update
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if (ctrl(ctrl_csr_we_c) = '1') then -- manual update
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| Line 1132... |
Line 1133... |
else -- automatic update by hardware
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else -- automatic update by hardware
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-- machine exception PC & exception value register --
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-- machine exception PC & exception value register --
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if (exc_cpu_ack = '1') then -- exception start?
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if (exc_cpu_ack = '1') then -- exception start?
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if (exc_cause(exc_cause_nxt'left) = '1') then -- for INTERRUPTs: mepc = address of next (unclompeted) instruction
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if (exc_cause(exc_cause_nxt'left) = '1') then -- for INTERRUPTs: mepc = address of next (unclompeted) instruction
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mepc <= pc_reg;
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mepc <= pc_reg;
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mtval <= (others => '-'); -- not specified
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mtval <= (others => '0'); -- not specified
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else -- for EXCEPTIONs: mepc = address of next (unclompeted) instruction
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else -- for EXCEPTIONs: mepc = address of next (unclompeted) instruction
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mepc <= pc_backup2_reg;
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mepc <= pc_backup2_reg;
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if ((exc_src(exception_iaccess_c) or exc_src(exception_ialign_c)) = '1') then -- instruction access error OR misaligned instruction
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if ((exc_src(exception_iaccess_c) or exc_src(exception_ialign_c)) = '1') then -- instruction access error OR misaligned instruction
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mtval <= pc_backup_reg;
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mtval <= pc_backup_reg;
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elsif (exc_src(exception_iillegal_c) = '1') then -- illegal instruction
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elsif (exc_src(exception_iillegal_c) = '1') then -- illegal instruction
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| Line 1250... |
Line 1251... |
csr_rdata_o(20) <= bool_to_ulogic_f(IO_TWI_USE); -- implement two-wire interface (TWI)?
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csr_rdata_o(20) <= bool_to_ulogic_f(IO_TWI_USE); -- implement two-wire interface (TWI)?
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csr_rdata_o(21) <= bool_to_ulogic_f(IO_PWM_USE); -- implement pulse-width modulation unit (PWM)?
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csr_rdata_o(21) <= bool_to_ulogic_f(IO_PWM_USE); -- implement pulse-width modulation unit (PWM)?
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csr_rdata_o(22) <= bool_to_ulogic_f(IO_WDT_USE); -- implement watch dog timer (WDT)?
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csr_rdata_o(22) <= bool_to_ulogic_f(IO_WDT_USE); -- implement watch dog timer (WDT)?
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csr_rdata_o(23) <= bool_to_ulogic_f(IO_CLIC_USE); -- implement core local interrupt controller (CLIC)?
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csr_rdata_o(23) <= bool_to_ulogic_f(IO_CLIC_USE); -- implement core local interrupt controller (CLIC)?
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csr_rdata_o(24) <= bool_to_ulogic_f(IO_TRNG_USE); -- implement true random number generator (TRNG)?
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csr_rdata_o(24) <= bool_to_ulogic_f(IO_TRNG_USE); -- implement true random number generator (TRNG)?
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csr_rdata_o(25) <= bool_to_ulogic_f(IO_DEVNULL_USE); -- implement dummy device (DEVNULL)?
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when x"fc1" => -- R/-: mclock - processor clock speed
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when x"fc1" => -- R/-: mclock - processor clock speed
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csr_rdata_o <= std_ulogic_vector(to_unsigned(CLOCK_FREQUENCY, 32));
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csr_rdata_o <= std_ulogic_vector(to_unsigned(CLOCK_FREQUENCY, 32));
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when x"fc4" => -- R/-: mispacebase - Base address of instruction memory space
|
when x"fc4" => -- R/-: mispacebase - Base address of instruction memory space
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csr_rdata_o <= MEM_ISPACE_BASE;
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csr_rdata_o <= MEM_ISPACE_BASE;
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when x"fc5" => -- R/-: mdspacebase - Base address of data memory space
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when x"fc5" => -- R/-: mdspacebase - Base address of data memory space
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