| Line 174... |
Line 174... |
state : execute_engine_state_t;
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state : execute_engine_state_t;
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state_prev : execute_engine_state_t;
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state_prev : execute_engine_state_t;
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state_nxt : execute_engine_state_t;
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state_nxt : execute_engine_state_t;
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i_reg : std_ulogic_vector(31 downto 0);
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i_reg : std_ulogic_vector(31 downto 0);
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i_reg_nxt : std_ulogic_vector(31 downto 0);
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i_reg_nxt : std_ulogic_vector(31 downto 0);
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i_reg_last : std_ulogic_vector(31 downto 0); -- last executed instruction
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is_ci : std_ulogic; -- current instruction is de-compressed instruction
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is_ci : std_ulogic; -- current instruction is de-compressed instruction
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is_ci_nxt : std_ulogic;
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is_ci_nxt : std_ulogic;
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is_jump : std_ulogic; -- current instruction is jump instruction
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is_jump : std_ulogic; -- current instruction is jump instruction
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is_jump_nxt : std_ulogic;
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is_jump_nxt : std_ulogic;
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is_cp_op : std_ulogic; -- current instruction is a co-processor operation
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is_cp_op : std_ulogic; -- current instruction is a co-processor operation
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| Line 657... |
Line 658... |
execute_engine.i_reg <= execute_engine.i_reg_nxt;
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execute_engine.i_reg <= execute_engine.i_reg_nxt;
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execute_engine.is_ci <= execute_engine.is_ci_nxt;
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execute_engine.is_ci <= execute_engine.is_ci_nxt;
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execute_engine.is_jump <= execute_engine.is_jump_nxt;
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execute_engine.is_jump <= execute_engine.is_jump_nxt;
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execute_engine.is_cp_op <= execute_engine.is_cp_op_nxt;
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execute_engine.is_cp_op <= execute_engine.is_cp_op_nxt;
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--
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--
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if (execute_engine.state = EXECUTE) then
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execute_engine.i_reg_last <= execute_engine.i_reg;
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end if;
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--
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ctrl <= ctrl_nxt;
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ctrl <= ctrl_nxt;
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end if;
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end if;
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end process execute_engine_fsm_sync;
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end process execute_engine_fsm_sync;
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-- next PC --
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-- next PC --
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| Line 782... |
Line 787... |
--
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--
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if (execute_engine.if_rst = '0') then -- if there was NO non-linear PC modification
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if (execute_engine.if_rst = '0') then -- if there was NO non-linear PC modification
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execute_engine.pc_nxt <= execute_engine.next_pc;
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execute_engine.pc_nxt <= execute_engine.next_pc;
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end if;
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end if;
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--
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--
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if (execute_engine.sleep = '1') or (trap_ctrl.env_start = '1') or ((i_buf.rdata(33) or i_buf.rdata(34)) = '1') then
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-- any reason to go FAST to trap state? --
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if (execute_engine.sleep = '1') or (trap_ctrl.env_start = '1') or (trap_ctrl.exc_fire = '1') or ((i_buf.rdata(33) or i_buf.rdata(34)) = '1') then
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execute_engine.state_nxt <= TRAP;
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execute_engine.state_nxt <= TRAP;
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else
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else
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execute_engine.state_nxt <= EXECUTE;
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execute_engine.state_nxt <= EXECUTE;
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end if;
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end if;
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end if;
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end if;
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| Line 844... |
Line 850... |
end if;
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end if;
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-- multi cycle alu operation? --
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-- multi cycle alu operation? --
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if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) or -- SLL shift operation?
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if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) or -- SLL shift operation?
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c) or -- SR shift operation?
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c) or -- SR shift operation?
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((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and (execute_engine.i_reg(instr_funct7_lsb_c) = '1')) then -- MULDIV?
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((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and (execute_engine.i_reg(instr_funct7_lsb_c) = '1') and (CPU_EXTENSION_RISCV_M = true)) then -- MULDIV?
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execute_engine.state_nxt <= ALU_WAIT;
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execute_engine.state_nxt <= ALU_WAIT;
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else -- single cycle ALU operation
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else -- single cycle ALU operation
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ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
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ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
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execute_engine.state_nxt <= DISPATCH;
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execute_engine.state_nxt <= DISPATCH;
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end if;
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end if;
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| Line 1617... |
Line 1623... |
(trap_ctrl.cause(4 downto 0) = trap_ima_c(4 downto 0)) or -- misaligned instruction address OR
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(trap_ctrl.cause(4 downto 0) = trap_ima_c(4 downto 0)) or -- misaligned instruction address OR
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(trap_ctrl.cause(4 downto 0) = trap_brk_c(4 downto 0)) or -- breakpoint OR
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(trap_ctrl.cause(4 downto 0) = trap_brk_c(4 downto 0)) or -- breakpoint OR
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(trap_ctrl.cause(4 downto 0) = trap_menv_c(4 downto 0)) then -- environment call
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(trap_ctrl.cause(4 downto 0) = trap_menv_c(4 downto 0)) then -- environment call
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csr.mtval <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- address of faulting instruction
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csr.mtval <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- address of faulting instruction
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elsif (trap_ctrl.cause(4 downto 0) = trap_iil_c(4 downto 0)) then -- illegal instruction
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elsif (trap_ctrl.cause(4 downto 0) = trap_iil_c(4 downto 0)) then -- illegal instruction
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csr.mtval <= execute_engine.i_reg; -- faulting instruction itself
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csr.mtval <= execute_engine.i_reg_last; -- faulting instruction itself
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else -- load/store misalignments/access errors
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else -- load/store misalignments/access errors
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csr.mtval <= mar_i; -- faulting data access address
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csr.mtval <= mar_i; -- faulting data access address
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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| Line 1845... |
Line 1851... |
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-- custom machine read-only CSRs --
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-- custom machine read-only CSRs --
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when csr_mzext_c => -- R/-: mzext
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when csr_mzext_c => -- R/-: mzext
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csr.rdata(0) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr); -- RISC-V.Zicsr CPU extension
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csr.rdata(0) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr); -- RISC-V.Zicsr CPU extension
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csr.rdata(1) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- RISC-V.Zifencei CPU extension
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csr.rdata(1) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- RISC-V.Zifencei CPU extension
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csr.rdata(2) <= bool_to_ulogic_f(PMP_USE); -- RISC-V physical memory protection
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-- undefined/unavailable --
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-- undefined/unavailable --
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when others =>
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when others =>
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csr.rdata <= (others => '0'); -- not implemented
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csr.rdata <= (others => '0'); -- not implemented
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