| Line 519... |
Line 519... |
-- ****************************************************************************************************************************
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-- ****************************************************************************************************************************
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-- Immediate Generator --------------------------------------------------------------------
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-- Immediate Generator --------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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imm_gen: process(clk_i)
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imm_gen: process(execute_engine.i_reg, clk_i)
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variable opcode_v : std_ulogic_vector(6 downto 0);
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variable opcode_v : std_ulogic_vector(6 downto 0);
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begin
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begin
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if rising_edge(clk_i) then
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opcode_v := execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c+2) & "11";
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opcode_v := execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c+2) & "11";
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if rising_edge(clk_i) then
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case opcode_v is -- save some bits here, LSBs are always 11 for rv32
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case opcode_v is -- save some bits here, LSBs are always 11 for rv32
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when opcode_store_c => -- S-immediate
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when opcode_store_c => -- S-immediate
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imm_o(31 downto 11) <= (others => execute_engine.i_reg(31)); -- sign extension
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imm_o(31 downto 11) <= (others => execute_engine.i_reg(31)); -- sign extension
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imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
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imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
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imm_o(04 downto 01) <= execute_engine.i_reg(11 downto 08);
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imm_o(04 downto 01) <= execute_engine.i_reg(11 downto 08);
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| Line 1231... |
Line 1231... |
-- any illegal condition? --
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-- any illegal condition? --
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trap_ctrl.instr_il <= illegal_instruction or illegal_opcode_lsbs or illegal_register or illegal_compressed;
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trap_ctrl.instr_il <= illegal_instruction or illegal_opcode_lsbs or illegal_register or illegal_compressed;
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-- ****************************************************************************************************************************
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-- ****************************************************************************************************************************
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-- Exception and Interrupt Control
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-- Exception and Interrupt (= Trap) Control
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-- ****************************************************************************************************************************
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-- ****************************************************************************************************************************
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-- Trap Controller ------------------------------------------------------------------------
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-- Trap Controller ------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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| Line 1303... |
Line 1303... |
begin
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begin
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-- defaults --
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-- defaults --
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trap_ctrl.cause_nxt <= (others => '0');
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trap_ctrl.cause_nxt <= (others => '0');
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trap_ctrl.irq_ack_nxt <= (others => '0');
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trap_ctrl.irq_ack_nxt <= (others => '0');
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-- the following traps are caused by asynchronous exceptions (-> interrupts)
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-- the following traps are caused by *asynchronous* exceptions (= interrupts)
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-- here we do need a specific acknowledge mask since several sources can trigger at once
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-- here we do need a specific acknowledge mask since several sources can trigger at once
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-- interrupt: 1.11 machine external interrupt --
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-- interrupt: 1.11 machine external interrupt --
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if (trap_ctrl.irq_buf(interrupt_mext_irq_c) = '1') then
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if (trap_ctrl.irq_buf(interrupt_mext_irq_c) = '1') then
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trap_ctrl.cause_nxt <= trap_mei_c;
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trap_ctrl.cause_nxt <= trap_mei_c;
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| Line 1343... |
Line 1343... |
elsif (trap_ctrl.irq_buf(interrupt_firq_3_c) = '1') then
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elsif (trap_ctrl.irq_buf(interrupt_firq_3_c) = '1') then
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trap_ctrl.cause_nxt <= trap_firq3_c;
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trap_ctrl.cause_nxt <= trap_firq3_c;
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trap_ctrl.irq_ack_nxt(interrupt_firq_3_c) <= '1';
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trap_ctrl.irq_ack_nxt(interrupt_firq_3_c) <= '1';
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-- the following traps are caused by synchronous exceptions
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-- the following traps are caused by *synchronous* exceptions (= classic exceptions)
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-- here we do not need a specific acknowledge mask since only one exception (the one
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-- here we do not need a specific acknowledge mask since only one exception (the one
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-- with highest priority) can trigger at once
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-- with highest priority) is evaluated at once
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-- trap/fault: 0.1 instruction access fault --
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-- exception: 0.1 instruction access fault --
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elsif (trap_ctrl.exc_buf(exception_iaccess_c) = '1') then
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elsif (trap_ctrl.exc_buf(exception_iaccess_c) = '1') then
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trap_ctrl.cause_nxt <= trap_iba_c;
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trap_ctrl.cause_nxt <= trap_iba_c;
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-- trap/fault: 0.2 illegal instruction --
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-- exception: 0.2 illegal instruction --
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elsif (trap_ctrl.exc_buf(exception_iillegal_c) = '1') then
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elsif (trap_ctrl.exc_buf(exception_iillegal_c) = '1') then
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trap_ctrl.cause_nxt <= trap_iil_c;
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trap_ctrl.cause_nxt <= trap_iil_c;
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-- trap/fault: 0.0 instruction address misaligned --
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-- exception: 0.0 instruction address misaligned --
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elsif (trap_ctrl.exc_buf(exception_ialign_c) = '1') then
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elsif (trap_ctrl.exc_buf(exception_ialign_c) = '1') then
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trap_ctrl.cause_nxt <= trap_ima_c;
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trap_ctrl.cause_nxt <= trap_ima_c;
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-- trap/fault: 0.11 environment call from M-mode --
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-- exception: 0.11 environment call from M-mode --
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elsif (trap_ctrl.exc_buf(exception_m_envcall_c) = '1') then
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elsif (trap_ctrl.exc_buf(exception_m_envcall_c) = '1') then
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trap_ctrl.cause_nxt <= trap_menv_c;
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trap_ctrl.cause_nxt <= trap_menv_c;
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-- trap/fault: 0.3 breakpoint --
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-- exception: 0.3 breakpoint --
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elsif (trap_ctrl.exc_buf(exception_break_c) = '1') then
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elsif (trap_ctrl.exc_buf(exception_break_c) = '1') then
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trap_ctrl.cause_nxt <= trap_brk_c;
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trap_ctrl.cause_nxt <= trap_brk_c;
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-- trap/fault: 0.6 store address misaligned -
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-- exception: 0.6 store address misaligned -
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elsif (trap_ctrl.exc_buf(exception_salign_c) = '1') then
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elsif (trap_ctrl.exc_buf(exception_salign_c) = '1') then
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trap_ctrl.cause_nxt <= trap_sma_c;
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trap_ctrl.cause_nxt <= trap_sma_c;
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-- trap/fault: 0.4 load address misaligned --
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-- exception: 0.4 load address misaligned --
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elsif (trap_ctrl.exc_buf(exception_lalign_c) = '1') then
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elsif (trap_ctrl.exc_buf(exception_lalign_c) = '1') then
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trap_ctrl.cause_nxt <= trap_lma_c;
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trap_ctrl.cause_nxt <= trap_lma_c;
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-- trap/fault: 0.7 store access fault --
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-- exception: 0.7 store access fault --
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elsif (trap_ctrl.exc_buf(exception_saccess_c) = '1') then
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elsif (trap_ctrl.exc_buf(exception_saccess_c) = '1') then
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trap_ctrl.cause_nxt <= trap_sbe_c;
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trap_ctrl.cause_nxt <= trap_sbe_c;
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-- trap/fault: 0.5 load access fault --
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-- exception: 0.5 load access fault --
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elsif (trap_ctrl.exc_buf(exception_laccess_c) = '1') then
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elsif (trap_ctrl.exc_buf(exception_laccess_c) = '1') then
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trap_ctrl.cause_nxt <= trap_lbe_c;
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trap_ctrl.cause_nxt <= trap_lbe_c;
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-- undefined / not implemented --
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-- undefined / not implemented --
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else
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else
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| Line 1405... |
Line 1405... |
variable csr_operand_v : std_ulogic_vector(data_width_c-1 downto 0);
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variable csr_operand_v : std_ulogic_vector(data_width_c-1 downto 0);
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begin
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begin
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-- CSR operand source --
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-- CSR operand source --
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if (execute_engine.i_reg(instr_funct3_msb_c) = '1') then -- immediate
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if (execute_engine.i_reg(instr_funct3_msb_c) = '1') then -- immediate
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csr_operand_v := (others => '0');
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csr_operand_v := (others => '0');
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csr_operand_v(4 downto 0) := execute_engine.i_reg(19 downto 15);
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csr_operand_v(4 downto 0) := execute_engine.i_reg(19 downto 15); -- uimm5
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else -- register
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else -- register
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csr_operand_v := rs1_i;
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csr_operand_v := rs1_i;
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end if;
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end if;
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-- "mini ALU" for CSR update operations --
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-- tiny ALU for CSR access operations --
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case execute_engine.i_reg(instr_funct3_lsb_c+1 downto instr_funct3_lsb_c) is
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case execute_engine.i_reg(instr_funct3_lsb_c+1 downto instr_funct3_lsb_c) is
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when "10" => csr.wdata <= csr.rdata or csr_operand_v; -- CSRRS(I)
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when "10" => csr.wdata <= csr.rdata or csr_operand_v; -- CSRRS(I)
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when "11" => csr.wdata <= csr.rdata and (not csr_operand_v); -- CSRRC(I)
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when "11" => csr.wdata <= csr.rdata and (not csr_operand_v); -- CSRRC(I)
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when others => csr.wdata <= csr_operand_v; -- CSRRW(I)
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when others => csr.wdata <= csr_operand_v; -- CSRRW(I)
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end case;
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end case;
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| Line 1678... |
Line 1678... |
csr.rdata(12) <= csr.mstatus_mpp(1); -- MPP: machine previous privilege mode high
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csr.rdata(12) <= csr.mstatus_mpp(1); -- MPP: machine previous privilege mode high
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when csr_misa_c => -- R/-: misa - ISA and extensions
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when csr_misa_c => -- R/-: misa - ISA and extensions
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csr.rdata(00) <= '0'; -- A CPU extension
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csr.rdata(00) <= '0'; -- A CPU extension
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csr.rdata(01) <= '0'; -- B CPU extension
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csr.rdata(01) <= '0'; -- B CPU extension
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csr.rdata(02) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_C); -- C CPU extension
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csr.rdata(02) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_C); -- C CPU extension
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csr.rdata(03) <= '0'; -- D CPU extension
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csr.rdata(04) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- E CPU extension
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csr.rdata(04) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- E CPU extension
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csr.rdata(05) <= '0'; -- F CPU extension
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csr.rdata(08) <= not bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- I CPU extension (if not E)
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csr.rdata(08) <= not bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- I CPU extension (if not E)
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csr.rdata(12) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_M); -- M CPU extension
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csr.rdata(12) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_M); -- M CPU extension
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csr.rdata(20) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_U); -- U CPU extension
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csr.rdata(20) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_U); -- U CPU extension
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csr.rdata(23) <= '1'; -- X CPU extension (non-std extensions)
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csr.rdata(23) <= '1'; -- X CPU extension (non-std extensions)
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csr.rdata(30) <= '1'; -- 32-bit architecture (MXL lo)
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csr.rdata(30) <= '1'; -- 32-bit architecture (MXL lo)
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