| Line 56... |
Line 56... |
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
|
-- Physical memory protection (PMP) --
|
-- Physical memory protection (PMP) --
|
PMP_USE : boolean := false; -- implement physical memory protection?
|
PMP_USE : boolean := false -- implement physical memory protection?
|
PMP_NUM_REGIONS : natural := 4; -- number of regions (1..4)
|
|
PMP_GRANULARITY : natural := 0 -- granularity (0=none, 1=8B, 2=16B, 3=32B, ...)
|
|
);
|
);
|
port (
|
port (
|
-- global control --
|
-- global control --
|
clk_i : in std_ulogic; -- global clock, rising edge
|
clk_i : in std_ulogic; -- global clock, rising edge
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
| Line 165... |
Line 163... |
|
|
-- instruction execution engine --
|
-- instruction execution engine --
|
type execute_engine_state_t is (SYS_WAIT, DISPATCH, TRAP, EXECUTE, ALU_WAIT, BRANCH, FENCE_OP, LOADSTORE_0, LOADSTORE_1, LOADSTORE_2, SYS_ENV, CSR_ACCESS);
|
type execute_engine_state_t is (SYS_WAIT, DISPATCH, TRAP, EXECUTE, ALU_WAIT, BRANCH, FENCE_OP, LOADSTORE_0, LOADSTORE_1, LOADSTORE_2, SYS_ENV, CSR_ACCESS);
|
type execute_engine_t is record
|
type execute_engine_t is record
|
state : execute_engine_state_t;
|
state : execute_engine_state_t;
|
state_prev : execute_engine_state_t;
|
|
state_nxt : execute_engine_state_t;
|
state_nxt : execute_engine_state_t;
|
--
|
--
|
i_reg : std_ulogic_vector(31 downto 0);
|
i_reg : std_ulogic_vector(31 downto 0);
|
i_reg_nxt : std_ulogic_vector(31 downto 0);
|
i_reg_nxt : std_ulogic_vector(31 downto 0);
|
i_reg_last : std_ulogic_vector(31 downto 0); -- last executed instruction
|
i_reg_last : std_ulogic_vector(31 downto 0); -- last executed instruction
|
--
|
--
|
is_ci : std_ulogic; -- current instruction is de-compressed instruction
|
is_ci : std_ulogic; -- current instruction is de-compressed instruction
|
is_ci_nxt : std_ulogic;
|
is_ci_nxt : std_ulogic;
|
is_jump : std_ulogic; -- current instruction is jump instruction
|
|
is_jump_nxt : std_ulogic;
|
|
is_cp_op : std_ulogic; -- current instruction is a co-processor operation
|
is_cp_op : std_ulogic; -- current instruction is a co-processor operation
|
is_cp_op_nxt : std_ulogic;
|
is_cp_op_nxt : std_ulogic;
|
--
|
--
|
branch_taken : std_ulogic; -- branch condition fullfilled
|
branch_taken : std_ulogic; -- branch condition fullfilled
|
pc : std_ulogic_vector(data_width_c-1 downto 0); -- actual PC, corresponding to current executed instruction
|
pc : std_ulogic_vector(data_width_c-1 downto 0); -- actual PC, corresponding to current executed instruction
|
| Line 202... |
Line 197... |
irq_buf : std_ulogic_vector(interrupt_width_c-1 downto 0);
|
irq_buf : std_ulogic_vector(interrupt_width_c-1 downto 0);
|
irq_fire : std_ulogic; -- set if there is a valid source in the interrupt buffer
|
irq_fire : std_ulogic; -- set if there is a valid source in the interrupt buffer
|
exc_ack : std_ulogic; -- acknowledge all exceptions
|
exc_ack : std_ulogic; -- acknowledge all exceptions
|
irq_ack : std_ulogic_vector(interrupt_width_c-1 downto 0); -- acknowledge specific interrupt
|
irq_ack : std_ulogic_vector(interrupt_width_c-1 downto 0); -- acknowledge specific interrupt
|
irq_ack_nxt : std_ulogic_vector(interrupt_width_c-1 downto 0);
|
irq_ack_nxt : std_ulogic_vector(interrupt_width_c-1 downto 0);
|
cause : std_ulogic_vector(5 downto 0); -- trap ID (for "mcause"), only for hw
|
cause : std_ulogic_vector(5 downto 0); -- trap ID for mcause CSR
|
cause_nxt : std_ulogic_vector(5 downto 0);
|
cause_nxt : std_ulogic_vector(5 downto 0);
|
--
|
--
|
env_start : std_ulogic; -- start trap handler env
|
env_start : std_ulogic; -- start trap handler env
|
env_start_ack : std_ulogic; -- start of trap handler acknowledged
|
env_start_ack : std_ulogic; -- start of trap handler acknowledged
|
env_end : std_ulogic; -- end trap handler env
|
env_end : std_ulogic; -- end trap handler env
|
| Line 227... |
Line 222... |
env_abort : std_ulogic; -- atomic operations abort (results in failure)
|
env_abort : std_ulogic; -- atomic operations abort (results in failure)
|
lock : std_ulogic; -- lock status
|
lock : std_ulogic; -- lock status
|
end record;
|
end record;
|
signal atomic_ctrl : atomic_ctrl_t;
|
signal atomic_ctrl : atomic_ctrl_t;
|
|
|
-- CPU control signals --
|
-- CPU main control bus --
|
signal ctrl_nxt, ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0);
|
signal ctrl_nxt, ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0);
|
|
|
-- fast bus access --
|
-- fast instruction fetch access --
|
signal bus_fast_ir : std_ulogic;
|
signal bus_fast_ir : std_ulogic;
|
|
|
-- RISC-V control and status registers (CSRs) --
|
-- RISC-V control and status registers (CSRs) --
|
type pmp_ctrl_t is array (0 to PMP_NUM_REGIONS-1) of std_ulogic_vector(7 downto 0);
|
type pmp_ctrl_t is array (0 to pmp_max_r_c-1) of std_ulogic_vector(7 downto 0);
|
type pmp_addr_t is array (0 to PMP_NUM_REGIONS-1) of std_ulogic_vector(data_width_c-1 downto 0);
|
type pmp_addr_t is array (0 to pmp_max_r_c-1) of std_ulogic_vector(data_width_c-1 downto 0);
|
type csr_t is record
|
type csr_t is record
|
we : std_ulogic; -- csr write enable
|
we : std_ulogic; -- csr write enable
|
we_nxt : std_ulogic;
|
we_nxt : std_ulogic;
|
re : std_ulogic; -- csr read enable
|
re : std_ulogic; -- csr read enable
|
re_nxt : std_ulogic;
|
re_nxt : std_ulogic;
|
wdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr write data
|
wdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr write data
|
rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
|
rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
|
--
|
--
|
mstatus_mie : std_ulogic; -- mstatus.MIE: global IRQ enable (R/W)
|
mstatus_mie : std_ulogic; -- mstatus.MIE: global IRQ enable (R/W)
|
mstatus_mpie : std_ulogic; -- mstatus.MPIE: previous global IRQ enable (R/-)
|
mstatus_mpie : std_ulogic; -- mstatus.MPIE: previous global IRQ enable (R/W)
|
mstatus_mpp : std_ulogic_vector(1 downto 0); -- mstatus.MPP: machine previous privilege mode
|
mstatus_mpp : std_ulogic_vector(1 downto 0); -- mstatus.MPP: machine previous privilege mode
|
--
|
--
|
mie_msie : std_ulogic; -- mie.MSIE: machine software interrupt enable (R/W)
|
mie_msie : std_ulogic; -- mie.MSIE: machine software interrupt enable (R/W)
|
mie_meie : std_ulogic; -- mie.MEIE: machine external interrupt enable (R/W)
|
mie_meie : std_ulogic; -- mie.MEIE: machine external interrupt enable (R/W)
|
mie_mtie : std_ulogic; -- mie.MEIE: machine timer interrupt enable (R/W
|
mie_mtie : std_ulogic; -- mie.MEIE: machine timer interrupt enable (R/W)
|
mie_firqe : std_ulogic_vector(3 downto 0); -- mie.firq*e: fast interrupt enabled (R/W)
|
mie_firqe : std_ulogic_vector(3 downto 0); -- mie.firq*e: fast interrupt enabled (R/W)
|
--
|
--
|
privilege : std_ulogic_vector(1 downto 0); -- hart's current previous privilege mode
|
mip_status : std_ulogic_vector(interrupt_width_c-1 downto 0); -- current buffered IRQs
|
|
mip_clear : std_ulogic_vector(interrupt_width_c-1 downto 0); -- set bits clear the according buffered IRQ
|
|
--
|
|
privilege : std_ulogic_vector(1 downto 0); -- hart's current privilege mode
|
|
priv_m_mode : std_ulogic; -- CPU in M-mode
|
|
priv_u_mode : std_ulogic; -- CPU in u-mode
|
--
|
--
|
mepc : std_ulogic_vector(data_width_c-1 downto 0); -- mepc: machine exception pc (R/W)
|
mepc : std_ulogic_vector(data_width_c-1 downto 0); -- mepc: machine exception pc (R/W)
|
mcause : std_ulogic_vector(data_width_c-1 downto 0); -- mcause: machine trap cause (R/-)
|
mcause : std_ulogic_vector(data_width_c-1 downto 0); -- mcause: machine trap cause (R/W)
|
mtvec : std_ulogic_vector(data_width_c-1 downto 0); -- mtvec: machine trap-handler base address (R/W), bit 1:0 == 00
|
mtvec : std_ulogic_vector(data_width_c-1 downto 0); -- mtvec: machine trap-handler base address (R/W), bit 1:0 == 00
|
mtval : std_ulogic_vector(data_width_c-1 downto 0); -- mtval: machine bad address or isntruction (R/W)
|
mtval : std_ulogic_vector(data_width_c-1 downto 0); -- mtval: machine bad address or isntruction (R/W)
|
mscratch : std_ulogic_vector(data_width_c-1 downto 0); -- mscratch: scratch register (R/W)
|
mscratch : std_ulogic_vector(data_width_c-1 downto 0); -- mscratch: scratch register (R/W)
|
mcycle : std_ulogic_vector(32 downto 0); -- mcycle (R/W), plus carry bit
|
mcycle : std_ulogic_vector(32 downto 0); -- mcycle (R/W), plus carry bit
|
minstret : std_ulogic_vector(32 downto 0); -- minstret (R/W), plus carry bit
|
minstret : std_ulogic_vector(32 downto 0); -- minstret (R/W), plus carry bit
|
mcycleh : std_ulogic_vector(31 downto 0); -- mcycleh (R/W) - REDUCED BIT-WIDTH!
|
mcycleh : std_ulogic_vector(31 downto 0); -- mcycleh (R/W)
|
minstreth : std_ulogic_vector(31 downto 0); -- minstreth (R/W) - REDUCED BIT-WIDTH!
|
minstreth : std_ulogic_vector(31 downto 0); -- minstreth (R/W)
|
pmpcfg : pmp_ctrl_t; -- physical memory protection - configuration registers
|
pmpcfg : pmp_ctrl_t; -- physical memory protection - configuration registers
|
pmpaddr : pmp_addr_t; -- physical memory protection - address registers
|
pmpaddr : pmp_addr_t; -- physical memory protection - address registers
|
end record;
|
end record;
|
signal csr : csr_t;
|
signal csr : csr_t;
|
|
|
| Line 406... |
Line 406... |
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
issue_engine_fsm_sync: process(rstn_i, clk_i)
|
issue_engine_fsm_sync: process(rstn_i, clk_i)
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
issue_engine.state <= ISSUE_ACTIVE;
|
issue_engine.state <= ISSUE_ACTIVE;
|
issue_engine.align <= CPU_BOOT_ADDR(1);
|
issue_engine.align <= CPU_BOOT_ADDR(1); -- 32- or 16-bit boundary
|
issue_engine.buf <= (others => '0');
|
issue_engine.buf <= (others => '0');
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
if (ipb.clear = '1') then
|
if (ipb.clear = '1') then
|
if (CPU_EXTENSION_RISCV_C = true) then
|
if (CPU_EXTENSION_RISCV_C = true) then
|
if (execute_engine.pc(1) = '1') then -- branch to unaligned address?
|
if (execute_engine.pc(1) = '1') then -- branch to unaligned address?
|
| Line 537... |
Line 537... |
imm_gen: process(execute_engine.i_reg, clk_i)
|
imm_gen: process(execute_engine.i_reg, clk_i)
|
variable opcode_v : std_ulogic_vector(6 downto 0);
|
variable opcode_v : std_ulogic_vector(6 downto 0);
|
begin
|
begin
|
opcode_v := execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c+2) & "11";
|
opcode_v := execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c+2) & "11";
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
if (execute_engine.state = BRANCH) then -- next_PC as immediate fro jump-and-link operations (=return address)
|
if (execute_engine.state = BRANCH) then -- next_PC as immediate for jump-and-link operations (=return address)
|
imm_o <= execute_engine.next_pc;
|
imm_o <= execute_engine.next_pc;
|
else -- "nromal" immediate from instruction
|
else -- "normal" immediate from instruction
|
case opcode_v is -- save some bits here, LSBs are always 11 for rv32
|
case opcode_v is -- save some bits here, LSBs are always 11 for rv32
|
when opcode_store_c => -- S-immediate
|
when opcode_store_c => -- S-immediate
|
imm_o(31 downto 11) <= (others => execute_engine.i_reg(31)); -- sign extension
|
imm_o(31 downto 11) <= (others => execute_engine.i_reg(31)); -- sign extension
|
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
|
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
|
imm_o(04 downto 01) <= execute_engine.i_reg(11 downto 08);
|
imm_o(04 downto 01) <= execute_engine.i_reg(11 downto 08);
|
| Line 564... |
Line 564... |
imm_o(11) <= execute_engine.i_reg(20);
|
imm_o(11) <= execute_engine.i_reg(20);
|
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
|
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
|
imm_o(04 downto 01) <= execute_engine.i_reg(24 downto 21);
|
imm_o(04 downto 01) <= execute_engine.i_reg(24 downto 21);
|
imm_o(00) <= '0';
|
imm_o(00) <= '0';
|
when opcode_atomic_c => -- atomic memory access
|
when opcode_atomic_c => -- atomic memory access
|
imm_o <= (others => '0'); -- effective address is reg + 0
|
imm_o <= (others => '0'); -- effective address is addr = reg + 0 = reg
|
when others => -- I-immediate
|
when others => -- I-immediate
|
imm_o(31 downto 11) <= (others => execute_engine.i_reg(31)); -- sign extension
|
imm_o(31 downto 11) <= (others => execute_engine.i_reg(31)); -- sign extension
|
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
|
imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
|
imm_o(04 downto 01) <= execute_engine.i_reg(24 downto 21);
|
imm_o(04 downto 01) <= execute_engine.i_reg(24 downto 21);
|
imm_o(00) <= execute_engine.i_reg(20);
|
imm_o(00) <= execute_engine.i_reg(20);
|
| Line 611... |
Line 611... |
-- PC update --
|
-- PC update --
|
if (execute_engine.pc_we = '1') then
|
if (execute_engine.pc_we = '1') then
|
case execute_engine.pc_mux_sel is
|
case execute_engine.pc_mux_sel is
|
when "00" => execute_engine.pc <= execute_engine.next_pc(data_width_c-1 downto 1) & '0'; -- normal (linear) increment
|
when "00" => execute_engine.pc <= execute_engine.next_pc(data_width_c-1 downto 1) & '0'; -- normal (linear) increment
|
when "01" => execute_engine.pc <= alu_add_i(data_width_c-1 downto 1) & '0'; -- jump/branch
|
when "01" => execute_engine.pc <= alu_add_i(data_width_c-1 downto 1) & '0'; -- jump/branch
|
when "10" => execute_engine.pc <= csr.mtvec(data_width_c-1 downto 1) & '0'; -- trap
|
when "10" => execute_engine.pc <= csr.mtvec(data_width_c-1 downto 1) & '0'; -- trap enter
|
when others => execute_engine.pc <= csr.mepc(data_width_c-1 downto 1) & '0'; -- trap return
|
when others => execute_engine.pc <= csr.mepc(data_width_c-1 downto 1) & '0'; -- trap return
|
end case;
|
end case;
|
end if;
|
end if;
|
--
|
--
|
execute_engine.state <= execute_engine.state_nxt;
|
execute_engine.state <= execute_engine.state_nxt;
|
| Line 627... |
Line 627... |
|
|
-- for registers that do NOT require a specific reset state --
|
-- for registers that do NOT require a specific reset state --
|
execute_engine_fsm_sync: process(clk_i)
|
execute_engine_fsm_sync: process(clk_i)
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
execute_engine.state_prev <= execute_engine.state;
|
|
execute_engine.i_reg <= execute_engine.i_reg_nxt;
|
execute_engine.i_reg <= execute_engine.i_reg_nxt;
|
execute_engine.is_ci <= execute_engine.is_ci_nxt;
|
execute_engine.is_ci <= execute_engine.is_ci_nxt;
|
execute_engine.is_jump <= execute_engine.is_jump_nxt;
|
|
execute_engine.is_cp_op <= execute_engine.is_cp_op_nxt;
|
execute_engine.is_cp_op <= execute_engine.is_cp_op_nxt;
|
-- next PC (next linear instruction) --
|
-- next PC (next linear instruction) --
|
|
if (execute_engine.state = EXECUTE) then
|
if (execute_engine.is_ci = '1') then -- compressed instruction?
|
if (execute_engine.is_ci = '1') then -- compressed instruction?
|
execute_engine.next_pc <= std_ulogic_vector(unsigned(execute_engine.pc) + 2);
|
execute_engine.next_pc <= std_ulogic_vector(unsigned(execute_engine.pc) + 2);
|
else
|
else
|
execute_engine.next_pc <= std_ulogic_vector(unsigned(execute_engine.pc) + 4);
|
execute_engine.next_pc <= std_ulogic_vector(unsigned(execute_engine.pc) + 4);
|
end if;
|
end if;
|
|
end if;
|
-- PC & IR of last "executed" instruction --
|
-- PC & IR of last "executed" instruction --
|
if (execute_engine.state = EXECUTE) then
|
if (execute_engine.state = EXECUTE) then
|
execute_engine.last_pc <= execute_engine.pc;
|
execute_engine.last_pc <= execute_engine.pc;
|
execute_engine.i_reg_last <= execute_engine.i_reg;
|
execute_engine.i_reg_last <= execute_engine.i_reg;
|
end if;
|
end if;
|
| Line 654... |
Line 654... |
curr_pc_o <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- PC for ALU ops
|
curr_pc_o <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- PC for ALU ops
|
|
|
|
|
-- CPU Control Bus Output -----------------------------------------------------------------
|
-- CPU Control Bus Output -----------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
ctrl_output: process(ctrl, fetch_engine, trap_ctrl, atomic_ctrl, bus_fast_ir, execute_engine, csr.privilege)
|
ctrl_output: process(ctrl, fetch_engine, trap_ctrl, atomic_ctrl, bus_fast_ir, execute_engine, csr)
|
begin
|
begin
|
-- signals from execute engine --
|
-- signals from execute engine --
|
ctrl_o <= ctrl;
|
ctrl_o <= ctrl;
|
-- current privilege level --
|
-- current privilege level --
|
ctrl_o(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c) <= csr.privilege;
|
ctrl_o(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c) <= csr.privilege;
|
| Line 690... |
Line 690... |
variable is_atomic_sc_v : std_ulogic;
|
variable is_atomic_sc_v : std_ulogic;
|
begin
|
begin
|
-- arbiter defaults --
|
-- arbiter defaults --
|
execute_engine.state_nxt <= execute_engine.state;
|
execute_engine.state_nxt <= execute_engine.state;
|
execute_engine.i_reg_nxt <= execute_engine.i_reg;
|
execute_engine.i_reg_nxt <= execute_engine.i_reg;
|
execute_engine.is_jump_nxt <= '0';
|
|
execute_engine.is_cp_op_nxt <= execute_engine.is_cp_op;
|
execute_engine.is_cp_op_nxt <= execute_engine.is_cp_op;
|
execute_engine.is_ci_nxt <= execute_engine.is_ci;
|
execute_engine.is_ci_nxt <= execute_engine.is_ci;
|
execute_engine.sleep_nxt <= execute_engine.sleep;
|
execute_engine.sleep_nxt <= execute_engine.sleep;
|
execute_engine.if_rst_nxt <= execute_engine.if_rst;
|
execute_engine.if_rst_nxt <= execute_engine.if_rst;
|
--
|
--
|
| Line 729... |
Line 728... |
if (execute_engine.i_reg(instr_opcode_lsb_c+4) = '1') then -- ALU ops
|
if (execute_engine.i_reg(instr_opcode_lsb_c+4) = '1') then -- ALU ops
|
ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+0); -- unsigned ALU operation? (SLTIU, SLTU)
|
ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+0); -- unsigned ALU operation? (SLTIU, SLTU)
|
else -- branches
|
else -- branches
|
ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1); -- unsigned branches? (BLTU, BGEU)
|
ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1); -- unsigned branches? (BLTU, BGEU)
|
end if;
|
end if;
|
-- memor access --
|
-- memory access --
|
ctrl_nxt(ctrl_bus_unsigned_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- unsigned LOAD (LBU, LHU)
|
ctrl_nxt(ctrl_bus_unsigned_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- unsigned LOAD (LBU, LHU)
|
ctrl_nxt(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1 downto instr_funct3_lsb_c); -- mem transfer size
|
ctrl_nxt(ctrl_bus_size_msb_c downto ctrl_bus_size_lsb_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1 downto instr_funct3_lsb_c); -- mem transfer size
|
-- alu.shifter --
|
-- alu.shifter --
|
ctrl_nxt(ctrl_alu_shift_dir_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- shift direction (left/right)
|
ctrl_nxt(ctrl_alu_shift_dir_c) <= execute_engine.i_reg(instr_funct3_msb_c); -- shift direction (left/right)
|
ctrl_nxt(ctrl_alu_shift_ar_c) <= execute_engine.i_reg(30); -- is arithmetic shift
|
ctrl_nxt(ctrl_alu_shift_ar_c) <= execute_engine.i_reg(30); -- is arithmetic shift
|
-- ALU control --
|
-- ALU main control --
|
ctrl_nxt(ctrl_alu_addsub_c) <= '0'; -- ADD(I)
|
ctrl_nxt(ctrl_alu_addsub_c) <= '0'; -- ADD(I)
|
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_arith_c; -- default ALU function select: arithmetic
|
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_arith_c; -- default ALU function select: arithmetic
|
ctrl_nxt(ctrl_alu_arith_c) <= alu_arith_cmd_addsub_c; -- default ALU arithmetic operation: ADDSUB
|
ctrl_nxt(ctrl_alu_arith_c) <= alu_arith_cmd_addsub_c; -- default ALU arithmetic operation: ADDSUB
|
ctrl_nxt(ctrl_alu_logic1_c downto ctrl_alu_logic0_c) <= alu_logic_cmd_movb_c; -- default ALU logic operation: MOVB
|
|
-- co-processor id --
|
|
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_muldiv_c; -- default CP = MULDIV
|
|
|
|
-- is immediate ALU operation? --
|
-- is immediate ALU operation? --
|
alu_immediate_v := not execute_engine.i_reg(instr_opcode_msb_c-1);
|
alu_immediate_v := not execute_engine.i_reg(instr_opcode_msb_c-1);
|
|
|
-- is rs1 == r0? --
|
-- is rs1 == r0? --
|
| Line 776... |
Line 772... |
|
|
|
|
when DISPATCH => -- Get new command from instruction issue engine
|
when DISPATCH => -- Get new command from instruction issue engine
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
execute_engine.pc_mux_sel <= "00"; -- linear next PC
|
execute_engine.pc_mux_sel <= "00"; -- linear next PC
|
if (cmd_issue.valid = '1') then -- instruction available?
|
|
-- IR update --
|
-- IR update --
|
execute_engine.is_ci_nxt <= cmd_issue.data(32); -- flag to indicate this is a de-compressed instruction beeing executed
|
execute_engine.is_ci_nxt <= cmd_issue.data(32); -- flag to indicate a de-compressed instruction beeing executed
|
execute_engine.i_reg_nxt <= cmd_issue.data(31 downto 0);
|
execute_engine.i_reg_nxt <= cmd_issue.data(31 downto 0);
|
|
--
|
|
if (cmd_issue.valid = '1') then -- instruction available?
|
|
-- IR update - exceptions --
|
trap_ctrl.instr_ma <= cmd_issue.data(33); -- misaligned instruction fetch address
|
trap_ctrl.instr_ma <= cmd_issue.data(33); -- misaligned instruction fetch address
|
trap_ctrl.instr_be <= cmd_issue.data(34); -- bus access fault during instrucion fetch
|
trap_ctrl.instr_be <= cmd_issue.data(34); -- bus access fault during instruction fetch
|
illegal_compressed <= cmd_issue.data(35); -- invalid decompressed instruction
|
illegal_compressed <= cmd_issue.data(35); -- invalid decompressed instruction
|
-- PC update --
|
-- PC update --
|
execute_engine.if_rst_nxt <= '0';
|
execute_engine.if_rst_nxt <= '0';
|
if (execute_engine.if_rst = '0') then -- if there was NO non-linear PC modification
|
execute_engine.pc_we <= not execute_engine.if_rst; -- update PC with linear next_pc if there was NO non-linear PC modification
|
execute_engine.pc_we <= '1';
|
-- any reason to go to trap state? --
|
end if;
|
|
-- any reason to go to trap state FAST? --
|
|
if (execute_engine.sleep = '1') or (trap_ctrl.env_start = '1') or (trap_ctrl.exc_fire = '1') or ((cmd_issue.data(33) or cmd_issue.data(34)) = '1') then
|
if (execute_engine.sleep = '1') or (trap_ctrl.env_start = '1') or (trap_ctrl.exc_fire = '1') or ((cmd_issue.data(33) or cmd_issue.data(34)) = '1') then
|
execute_engine.state_nxt <= TRAP;
|
execute_engine.state_nxt <= TRAP;
|
else
|
else
|
execute_engine.state_nxt <= EXECUTE;
|
execute_engine.state_nxt <= EXECUTE;
|
end if;
|
end if;
|
| Line 800... |
Line 796... |
|
|
|
|
when TRAP => -- Start trap environment (also used as cpu sleep state)
|
when TRAP => -- Start trap environment (also used as cpu sleep state)
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
execute_engine.pc_mux_sel <= "10"; -- csr.mtvec (trap)
|
execute_engine.pc_mux_sel <= "10"; -- csr.mtvec (trap)
|
-- stay here for sleep
|
|
if (trap_ctrl.env_start = '1') then -- trap triggered?
|
|
fetch_engine.reset <= '1';
|
fetch_engine.reset <= '1';
|
execute_engine.if_rst_nxt <= '1'; -- this is a non-linear PC modification
|
execute_engine.if_rst_nxt <= '1'; -- this will be a non-linear PC modification
|
|
if (trap_ctrl.env_start = '1') then -- trap triggered?
|
trap_ctrl.env_start_ack <= '1';
|
trap_ctrl.env_start_ack <= '1';
|
execute_engine.pc_we <= '1';
|
execute_engine.pc_we <= '1';
|
execute_engine.sleep_nxt <= '0'; -- waky waky
|
execute_engine.sleep_nxt <= '0'; -- waky waky
|
execute_engine.state_nxt <= SYS_WAIT;
|
execute_engine.state_nxt <= SYS_WAIT;
|
end if;
|
end if;
|
|
|
|
|
when EXECUTE => -- Decode and execute instruction
|
when EXECUTE => -- Decode and execute instruction (control has to be here for excatly 1 cyle in any case!)
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
opcode_v := execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c+2) & "11"; -- save some bits here, LSBs are always 11 for rv32
|
opcode_v := execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c+2) & "11"; -- save some bits here, LSBs are always 11 for rv32
|
case opcode_v is
|
case opcode_v is
|
|
|
when opcode_alu_c | opcode_alui_c => -- (immediate) ALU operation
|
when opcode_alu_c | opcode_alui_c => -- (immediate) ALU operation
|
| Line 843... |
Line 838... |
|
|
-- ALU logic operation --
|
-- ALU logic operation --
|
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is -- actual ALU.logic operation (re-coding)
|
case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is -- actual ALU.logic operation (re-coding)
|
when funct3_xor_c => ctrl_nxt(ctrl_alu_logic1_c downto ctrl_alu_logic0_c) <= alu_logic_cmd_xor_c; -- XOR(I)
|
when funct3_xor_c => ctrl_nxt(ctrl_alu_logic1_c downto ctrl_alu_logic0_c) <= alu_logic_cmd_xor_c; -- XOR(I)
|
when funct3_or_c => ctrl_nxt(ctrl_alu_logic1_c downto ctrl_alu_logic0_c) <= alu_logic_cmd_or_c; -- OR(I)
|
when funct3_or_c => ctrl_nxt(ctrl_alu_logic1_c downto ctrl_alu_logic0_c) <= alu_logic_cmd_or_c; -- OR(I)
|
when funct3_and_c => ctrl_nxt(ctrl_alu_logic1_c downto ctrl_alu_logic0_c) <= alu_logic_cmd_and_c; -- AND(I)
|
when others => ctrl_nxt(ctrl_alu_logic1_c downto ctrl_alu_logic0_c) <= alu_logic_cmd_and_c; -- AND(I)
|
when others => ctrl_nxt(ctrl_alu_logic1_c downto ctrl_alu_logic0_c) <= alu_logic_cmd_movb_c; -- undefined
|
|
end case;
|
end case;
|
|
|
-- cp access? --
|
-- cp access? --
|
|
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_muldiv_c; -- just in case a mul/div operation
|
if (CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and (execute_engine.i_reg(instr_funct7_lsb_c) = '1') then -- MULDIV CP op?
|
if (CPU_EXTENSION_RISCV_M = true) and (execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and (execute_engine.i_reg(instr_funct7_lsb_c) = '1') then -- MULDIV CP op?
|
execute_engine.is_cp_op_nxt <= '1'; -- this is a CP operation
|
execute_engine.is_cp_op_nxt <= '1'; -- this is a CP operation
|
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_copro_c;
|
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_copro_c;
|
-- ALU operation - function select --
|
-- ALU operation - function select --
|
else
|
else
|
| Line 916... |
Line 911... |
else -- JAL / branch
|
else -- JAL / branch
|
ctrl_nxt(ctrl_alu_opa_mux_c) <= '1'; -- use PC as ALU.OPA (branch target address base)
|
ctrl_nxt(ctrl_alu_opa_mux_c) <= '1'; -- use PC as ALU.OPA (branch target address base)
|
end if;
|
end if;
|
ctrl_nxt(ctrl_alu_opb_mux_c) <= '1'; -- use IMM as ALU.OPB (branch target address offset)
|
ctrl_nxt(ctrl_alu_opb_mux_c) <= '1'; -- use IMM as ALU.OPB (branch target address offset)
|
--
|
--
|
execute_engine.is_jump_nxt <= execute_engine.i_reg(instr_opcode_lsb_c+2); -- is this is a jump operation? (for JAL/JALR)
|
|
execute_engine.state_nxt <= BRANCH;
|
execute_engine.state_nxt <= BRANCH;
|
|
|
when opcode_fence_c => -- fence operations
|
when opcode_fence_c => -- fence operations
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
execute_engine.state_nxt <= FENCE_OP;
|
execute_engine.state_nxt <= FENCE_OP;
|
|
|
when opcode_syscsr_c => -- system/csr access
|
when opcode_syscsr_c => -- system/csr access
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
csr.re_nxt <= '1'; -- always read CSR (internally), only relevant for CSR-instructions
|
csr.re_nxt <= csr_acc_valid; -- always read CSR if valid access, only relevant for CSR-instructions
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_env_c) then -- system/environment
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_env_c) then -- system/environment
|
execute_engine.state_nxt <= SYS_ENV;
|
execute_engine.state_nxt <= SYS_ENV;
|
else -- CSR access
|
else -- CSR access
|
execute_engine.state_nxt <= CSR_ACCESS;
|
execute_engine.state_nxt <= CSR_ACCESS;
|
end if;
|
end if;
|
| Line 941... |
Line 935... |
end case;
|
end case;
|
|
|
|
|
when SYS_ENV => -- system environment operation - execution
|
when SYS_ENV => -- system environment operation - execution
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
execute_engine.pc_mux_sel <= "11"; -- csr.mepc (only for MRET)
|
execute_engine.pc_mux_sel <= "11"; -- csr.mepc (only relevant for MRET)
|
case execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) is
|
case execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) is
|
when funct12_ecall_c => -- ECALL
|
when funct12_ecall_c => -- ECALL
|
trap_ctrl.env_call <= '1';
|
trap_ctrl.env_call <= '1';
|
when funct12_ebreak_c => -- EBREAK
|
when funct12_ebreak_c => -- EBREAK
|
trap_ctrl.break_point <= '1';
|
trap_ctrl.break_point <= '1';
|
when funct12_mret_c => -- MRET
|
when funct12_mret_c => -- MRET
|
trap_ctrl.env_end <= '1';
|
trap_ctrl.env_end <= '1';
|
execute_engine.pc_we <= '1'; -- linear next PC
|
execute_engine.pc_we <= '1'; -- update PC from MEPC
|
fetch_engine.reset <= '1';
|
fetch_engine.reset <= '1';
|
execute_engine.if_rst_nxt <= '1'; -- this is a non-linear PC modification
|
execute_engine.if_rst_nxt <= '1'; -- this is a non-linear PC modification
|
when funct12_wfi_c => -- WFI
|
when funct12_wfi_c => -- WFI
|
execute_engine.sleep_nxt <= '1'; -- good night
|
execute_engine.sleep_nxt <= '1'; -- good night
|
when others => -- undefined
|
when others => -- undefined
|
| Line 1000... |
Line 994... |
-- get and store return address (only relevant for jump-and-link operations) --
|
-- get and store return address (only relevant for jump-and-link operations) --
|
ctrl_nxt(ctrl_alu_opb_mux_c) <= '1'; -- use IMM as ALU.OPB (next_pc from immediate generator = return address)
|
ctrl_nxt(ctrl_alu_opb_mux_c) <= '1'; -- use IMM as ALU.OPB (next_pc from immediate generator = return address)
|
ctrl_nxt(ctrl_alu_logic1_c downto ctrl_alu_logic0_c) <= alu_logic_cmd_movb_c; -- MOVB
|
ctrl_nxt(ctrl_alu_logic1_c downto ctrl_alu_logic0_c) <= alu_logic_cmd_movb_c; -- MOVB
|
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_logic_c; -- actual ALU operation = MOVB
|
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_logic_c; -- actual ALU operation = MOVB
|
ctrl_nxt(ctrl_rf_in_mux_msb_c) <= '0'; -- RF input = ALU result
|
ctrl_nxt(ctrl_rf_in_mux_msb_c) <= '0'; -- RF input = ALU result
|
ctrl_nxt(ctrl_rf_wb_en_c) <= execute_engine.is_jump; -- valid RF write-back? (is jump-and-link?)
|
ctrl_nxt(ctrl_rf_wb_en_c) <= execute_engine.i_reg(instr_opcode_lsb_c+2); -- valid RF write-back? (is jump-and-link?)
|
-- destination address --
|
-- destination address --
|
execute_engine.pc_mux_sel <= "01"; -- alu.add = branch/jump destination
|
execute_engine.pc_mux_sel <= "01"; -- alu.add = branch/jump destination
|
if (execute_engine.is_jump = '1') or (execute_engine.branch_taken = '1') then
|
if (execute_engine.i_reg(instr_opcode_lsb_c+2) = '1') or (execute_engine.branch_taken = '1') then -- JAL/JALR or taken branch
|
execute_engine.pc_we <= '1'; -- update PC
|
execute_engine.pc_we <= '1'; -- update PC
|
fetch_engine.reset <= '1'; -- trigger new instruction fetch from modified PC
|
fetch_engine.reset <= '1'; -- trigger new instruction fetch from modified PC
|
execute_engine.if_rst_nxt <= '1'; -- this is a non-linear PC modification
|
execute_engine.if_rst_nxt <= '1'; -- this is a non-linear PC modification
|
execute_engine.state_nxt <= SYS_WAIT;
|
execute_engine.state_nxt <= SYS_WAIT;
|
else
|
else
|
| Line 1016... |
Line 1010... |
|
|
|
|
when FENCE_OP => -- fence operations - execution
|
when FENCE_OP => -- fence operations - execution
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
execute_engine.state_nxt <= SYS_WAIT;
|
execute_engine.state_nxt <= SYS_WAIT;
|
execute_engine.pc_mux_sel <= "00"; -- linear next PC = "refetch" next instruction
|
execute_engine.pc_mux_sel <= "00"; -- linear next PC = "refetch" next instruction (only relevant for fence.i)
|
-- FENCE.I --
|
-- FENCE.I --
|
if (execute_engine.i_reg(instr_funct3_lsb_c) = funct3_fencei_c(0)) and (CPU_EXTENSION_RISCV_Zifencei = true) then
|
if (execute_engine.i_reg(instr_funct3_lsb_c) = funct3_fencei_c(0)) and (CPU_EXTENSION_RISCV_Zifencei = true) then
|
execute_engine.pc_we <= '1';
|
execute_engine.pc_we <= '1';
|
execute_engine.if_rst_nxt <= '1'; -- this is a non-linear PC modification
|
execute_engine.if_rst_nxt <= '1'; -- this is a non-linear PC modification
|
fetch_engine.reset <= '1';
|
fetch_engine.reset <= '1';
|
| Line 1048... |
Line 1042... |
execute_engine.state_nxt <= LOADSTORE_2;
|
execute_engine.state_nxt <= LOADSTORE_2;
|
|
|
|
|
when LOADSTORE_2 => -- wait for bus transaction to finish
|
when LOADSTORE_2 => -- wait for bus transaction to finish
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
if (CPU_EXTENSION_RISCV_A = true) then -- only relevant for atomic operations
|
-- ALU control (only relevant for atomic memory operations) --
|
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_atomic_c; -- SC: result comes from "atomic co-processor"
|
if (CPU_EXTENSION_RISCV_A = true) then
|
|
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_atomic_c; -- atomic.SC: result comes from "atomic co-processor"
|
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_copro_c;
|
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_copro_c;
|
end if;
|
end if;
|
--
|
-- register file write-back --
|
ctrl_nxt(ctrl_rf_in_mux_lsb_c) <= '0'; -- RF input = ALU.res or MEM
|
ctrl_nxt(ctrl_rf_in_mux_lsb_c) <= '0'; -- RF input = ALU.res or MEM
|
if (is_atomic_sc_v = '1') then
|
if (is_atomic_sc_v = '1') then
|
ctrl_nxt(ctrl_rf_in_mux_msb_c) <= '0'; -- RF input = ALU.res
|
ctrl_nxt(ctrl_rf_in_mux_msb_c) <= '0'; -- RF input = ALU.res (only relevant for atomic.SC)
|
else
|
else
|
ctrl_nxt(ctrl_rf_in_mux_msb_c) <= '1'; -- RF input = memory input (only relevant for LOAD)
|
ctrl_nxt(ctrl_rf_in_mux_msb_c) <= '1'; -- RF input = memory input (only relevant for LOADs)
|
end if;
|
end if;
|
--
|
--
|
ctrl_nxt(ctrl_bus_mi_we_c) <= '1'; -- keep writing input data to MDI (only relevant for load operations)
|
ctrl_nxt(ctrl_bus_mi_we_c) <= '1'; -- keep writing input data to MDI (only relevant for load operations)
|
-- wait for memory response --
|
-- wait for memory response --
|
if ((ma_load_i or be_load_i or ma_store_i or be_store_i) = '1') then -- abort if exception
|
if ((ma_load_i or be_load_i or ma_store_i or be_store_i) = '1') then -- abort if exception
|
| Line 1090... |
Line 1085... |
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
|
|
|
|
-- Illegal CSR Access Check ---------------------------------------------------------------
|
-- Illegal CSR Access Check ---------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
invalid_csr_access_check: process(execute_engine.i_reg, csr.privilege)
|
invalid_csr_access_check: process(execute_engine.i_reg, csr)
|
variable is_m_mode_v : std_ulogic;
|
|
variable csr_wacc_v : std_ulogic; -- to check access to read-only CSRs
|
variable csr_wacc_v : std_ulogic; -- to check access to read-only CSRs
|
-- variable csr_racc_v : std_ulogic; -- to check access to write-only CSRs
|
-- variable csr_racc_v : std_ulogic; -- to check access to write-only CSRs
|
begin
|
begin
|
-- are we in machine mode? --
|
|
if (csr.privilege = priv_mode_m_c) then
|
|
is_m_mode_v := '1';
|
|
else
|
|
is_m_mode_v := '0';
|
|
end if;
|
|
|
|
-- is this CSR instruction really going to write/read to/from a CSR? --
|
-- is this CSR instruction really going to write/read to/from a CSR? --
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrwi_c) then
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrwi_c) then
|
csr_wacc_v := '1'; -- always write CSR
|
csr_wacc_v := '1'; -- always write CSR
|
-- csr_racc_v := or_all_f(execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c)); -- read allowed if rd != 0
|
-- csr_racc_v := or_all_f(execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c)); -- read allowed if rd != 0
|
| Line 1114... |
Line 1101... |
-- csr_racc_v := '1'; -- always read CSR
|
-- csr_racc_v := '1'; -- always read CSR
|
end if;
|
end if;
|
|
|
-- check CSR access --
|
-- check CSR access --
|
case execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) is
|
case execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) is
|
when csr_mstatus_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
|
when csr_mstatus_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
when csr_misa_c => csr_acc_valid <= is_m_mode_v;-- and (not csr_wacc_v); -- M-mode only, MISA is read-only in the NEORV32 but we don't cause an exception here for compatibility
|
when csr_mstatush_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
when csr_mie_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
|
when csr_misa_c => csr_acc_valid <= csr.priv_m_mode;-- and (not csr_wacc_v); -- M-mode only, MISA is read-only in the NEORV32 but we don't cause an exception here for compatibility
|
when csr_mtvec_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
|
when csr_mie_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
when csr_mscratch_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
|
when csr_mtvec_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
when csr_mepc_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
|
when csr_mscratch_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
when csr_mcause_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
|
when csr_mepc_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
when csr_mtval_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
|
when csr_mcause_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
when csr_mip_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
|
when csr_mtval_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
--
|
when csr_mip_c => csr_acc_valid <= csr.priv_m_mode; -- M-mode only
|
when csr_pmpcfg0_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 1)) and is_m_mode_v; -- M-mode only
|
--
|
when csr_pmpcfg1_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 5)) and is_m_mode_v; -- M-mode only
|
when csr_pmpcfg0_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 1)) and csr.priv_m_mode; -- M-mode only
|
--
|
when csr_pmpcfg1_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 5)) and csr.priv_m_mode; -- M-mode only
|
when csr_pmpaddr0_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 1)) and is_m_mode_v; -- M-mode only
|
--
|
when csr_pmpaddr1_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 2)) and is_m_mode_v; -- M-mode only
|
when csr_pmpaddr0_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 1)) and csr.priv_m_mode; -- M-mode only
|
when csr_pmpaddr2_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 3)) and is_m_mode_v; -- M-mode only
|
when csr_pmpaddr1_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 2)) and csr.priv_m_mode; -- M-mode only
|
when csr_pmpaddr3_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 4)) and is_m_mode_v; -- M-mode only
|
when csr_pmpaddr2_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 3)) and csr.priv_m_mode; -- M-mode only
|
when csr_pmpaddr4_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 5)) and is_m_mode_v; -- M-mode only
|
when csr_pmpaddr3_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 4)) and csr.priv_m_mode; -- M-mode only
|
when csr_pmpaddr5_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 6)) and is_m_mode_v; -- M-mode only
|
when csr_pmpaddr4_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 5)) and csr.priv_m_mode; -- M-mode only
|
when csr_pmpaddr6_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 7)) and is_m_mode_v; -- M-mode only
|
when csr_pmpaddr5_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 6)) and csr.priv_m_mode; -- M-mode only
|
when csr_pmpaddr7_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(PMP_NUM_REGIONS >= 8)) and is_m_mode_v; -- M-mode only
|
when csr_pmpaddr6_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 7)) and csr.priv_m_mode; -- M-mode only
|
|
when csr_pmpaddr7_c => csr_acc_valid <= bool_to_ulogic_f(PMP_USE) and bool_to_ulogic_f(boolean(pmp_num_regions_c >= 8)) and csr.priv_m_mode; -- M-mode only
|
--
|
--
|
when csr_mcycle_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
|
when csr_mcycle_c => csr_acc_valid <= csr.priv_m_mode and bool_to_ulogic_f(zicnt_en_c); -- M-mode only and "Zicnt" = true
|
when csr_minstret_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
|
when csr_minstret_c => csr_acc_valid <= csr.priv_m_mode and bool_to_ulogic_f(zicnt_en_c); -- M-mode only and "Zicnt" = true
|
--
|
--
|
when csr_mcycleh_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
|
when csr_mcycleh_c => csr_acc_valid <= csr.priv_m_mode and bool_to_ulogic_f(zicnt_en_c); -- M-mode only and "Zicnt" = true
|
when csr_minstreth_c => csr_acc_valid <= is_m_mode_v; -- M-mode only
|
when csr_minstreth_c => csr_acc_valid <= csr.priv_m_mode and bool_to_ulogic_f(zicnt_en_c); -- M-mode only and "Zicnt" = true
|
--
|
--
|
when csr_cycle_c => csr_acc_valid <= (not csr_wacc_v); -- all modes, read-only
|
when csr_cycle_c => csr_acc_valid <= (not csr_wacc_v) and bool_to_ulogic_f(zicnt_en_c); -- all modes, read-only and "Zicnt" = true
|
when csr_time_c => csr_acc_valid <= (not csr_wacc_v); -- all modes, read-only
|
when csr_time_c => csr_acc_valid <= (not csr_wacc_v); -- all modes, read-only
|
when csr_instret_c => csr_acc_valid <= (not csr_wacc_v); -- all modes, read-only
|
when csr_instret_c => csr_acc_valid <= (not csr_wacc_v) and bool_to_ulogic_f(zicnt_en_c); -- all modes, read-only and "Zicnt" = true
|
--
|
--
|
when csr_cycleh_c => csr_acc_valid <= (not csr_wacc_v); -- all modes, read-only
|
when csr_cycleh_c => csr_acc_valid <= (not csr_wacc_v) and bool_to_ulogic_f(zicnt_en_c); -- all modes, read-only and "Zicnt" = true
|
when csr_timeh_c => csr_acc_valid <= (not csr_wacc_v); -- all modes, read-only
|
when csr_timeh_c => csr_acc_valid <= (not csr_wacc_v); -- all modes, read-only
|
when csr_instreth_c => csr_acc_valid <= (not csr_wacc_v); -- all modes, read-only
|
when csr_instreth_c => csr_acc_valid <= (not csr_wacc_v) and bool_to_ulogic_f(zicnt_en_c); -- all modes, read-only and "Zicnt" = true
|
--
|
--
|
when csr_mvendorid_c => csr_acc_valid <= is_m_mode_v and (not csr_wacc_v); -- M-mode only, read-only
|
when csr_mvendorid_c => csr_acc_valid <= csr.priv_m_mode and (not csr_wacc_v); -- M-mode only, read-only
|
when csr_marchid_c => csr_acc_valid <= is_m_mode_v and (not csr_wacc_v); -- M-mode only, read-only
|
when csr_marchid_c => csr_acc_valid <= csr.priv_m_mode and (not csr_wacc_v); -- M-mode only, read-only
|
when csr_mimpid_c => csr_acc_valid <= is_m_mode_v and (not csr_wacc_v); -- M-mode only, read-only
|
when csr_mimpid_c => csr_acc_valid <= csr.priv_m_mode and (not csr_wacc_v); -- M-mode only, read-only
|
when csr_mhartid_c => csr_acc_valid <= is_m_mode_v and (not csr_wacc_v); -- M-mode only, read-only
|
when csr_mhartid_c => csr_acc_valid <= csr.priv_m_mode and (not csr_wacc_v); -- M-mode only, read-only
|
--
|
--
|
when csr_mzext_c => csr_acc_valid <= is_m_mode_v and (not csr_wacc_v); -- M-mode only, read-only
|
when csr_mzext_c => csr_acc_valid <= csr.priv_m_mode and (not csr_wacc_v); -- M-mode only, read-only
|
--
|
--
|
when others => csr_acc_valid <= '0'; -- undefined, invalid access
|
when others => csr_acc_valid <= '0'; -- undefined, invalid access
|
end case;
|
end case;
|
end process invalid_csr_access_check;
|
end process invalid_csr_access_check;
|
|
|
| Line 1361... |
Line 1349... |
|
|
|
|
-- Trap Controller ------------------------------------------------------------------------
|
-- Trap Controller ------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
trap_controller: process(rstn_i, clk_i)
|
trap_controller: process(rstn_i, clk_i)
|
|
variable mode_m_v, mode_u_v : std_ulogic;
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
trap_ctrl.exc_buf <= (others => '0');
|
trap_ctrl.exc_buf <= (others => '0');
|
trap_ctrl.irq_buf <= (others => '0');
|
trap_ctrl.irq_buf <= (others => '0');
|
trap_ctrl.exc_ack <= '0';
|
trap_ctrl.exc_ack <= '0';
|
trap_ctrl.irq_ack <= (others => '0');
|
trap_ctrl.irq_ack <= (others => '0');
|
trap_ctrl.cause <= (others => '0');
|
trap_ctrl.cause <= trap_reset_c;
|
trap_ctrl.env_start <= '0';
|
trap_ctrl.env_start <= '0';
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
if (CPU_EXTENSION_RISCV_Zicsr = true) then
|
if (CPU_EXTENSION_RISCV_Zicsr = true) then
|
-- exception buffer: misaligned load/store/instruction address
|
-- exception buffer: misaligned load/store/instruction address
|
trap_ctrl.exc_buf(exception_lalign_c) <= (trap_ctrl.exc_buf(exception_lalign_c) or ma_load_i) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_lalign_c) <= (trap_ctrl.exc_buf(exception_lalign_c) or ma_load_i) and (not trap_ctrl.exc_ack);
|
| Line 1380... |
Line 1369... |
-- exception buffer: load/store/instruction bus access error
|
-- exception buffer: load/store/instruction bus access error
|
trap_ctrl.exc_buf(exception_laccess_c) <= (trap_ctrl.exc_buf(exception_laccess_c) or be_load_i) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_laccess_c) <= (trap_ctrl.exc_buf(exception_laccess_c) or be_load_i) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_saccess_c) <= (trap_ctrl.exc_buf(exception_saccess_c) or be_store_i) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_saccess_c) <= (trap_ctrl.exc_buf(exception_saccess_c) or be_store_i) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_iaccess_c) <= (trap_ctrl.exc_buf(exception_iaccess_c) or trap_ctrl.instr_be) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_iaccess_c) <= (trap_ctrl.exc_buf(exception_iaccess_c) or trap_ctrl.instr_be) and (not trap_ctrl.exc_ack);
|
-- exception buffer: illegal instruction / env call / break point
|
-- exception buffer: illegal instruction / env call / break point
|
trap_ctrl.exc_buf(exception_m_envcall_c) <= (trap_ctrl.exc_buf(exception_m_envcall_c) or trap_ctrl.env_call) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_m_envcall_c) <= (trap_ctrl.exc_buf(exception_m_envcall_c) or (trap_ctrl.env_call and csr.priv_m_mode)) and (not trap_ctrl.exc_ack);
|
|
trap_ctrl.exc_buf(exception_u_envcall_c) <= (trap_ctrl.exc_buf(exception_u_envcall_c) or (trap_ctrl.env_call and csr.priv_u_mode)) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_break_c) <= (trap_ctrl.exc_buf(exception_break_c) or trap_ctrl.break_point) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_break_c) <= (trap_ctrl.exc_buf(exception_break_c) or trap_ctrl.break_point) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_iillegal_c) <= (trap_ctrl.exc_buf(exception_iillegal_c) or trap_ctrl.instr_il) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_iillegal_c) <= (trap_ctrl.exc_buf(exception_iillegal_c) or trap_ctrl.instr_il) and (not trap_ctrl.exc_ack);
|
-- interrupt buffer: machine software/external/timer interrupt
|
-- interrupt buffer: machine software/external/timer interrupt
|
trap_ctrl.irq_buf(interrupt_msw_irq_c) <= csr.mie_msie and (trap_ctrl.irq_buf(interrupt_msw_irq_c) or msw_irq_i) and (not trap_ctrl.irq_ack(interrupt_msw_irq_c));
|
trap_ctrl.irq_buf(interrupt_msw_irq_c) <= csr.mie_msie and (trap_ctrl.irq_buf(interrupt_msw_irq_c) or msw_irq_i) and (not (trap_ctrl.irq_ack(interrupt_msw_irq_c) or csr.mip_clear(interrupt_msw_irq_c)));
|
trap_ctrl.irq_buf(interrupt_mext_irq_c) <= csr.mie_meie and (trap_ctrl.irq_buf(interrupt_mext_irq_c) or mext_irq_i) and (not trap_ctrl.irq_ack(interrupt_mext_irq_c));
|
trap_ctrl.irq_buf(interrupt_mext_irq_c) <= csr.mie_meie and (trap_ctrl.irq_buf(interrupt_mext_irq_c) or mext_irq_i) and (not (trap_ctrl.irq_ack(interrupt_mext_irq_c) or csr.mip_clear(interrupt_mext_irq_c)));
|
trap_ctrl.irq_buf(interrupt_mtime_irq_c) <= csr.mie_mtie and (trap_ctrl.irq_buf(interrupt_mtime_irq_c) or mtime_irq_i) and (not trap_ctrl.irq_ack(interrupt_mtime_irq_c));
|
trap_ctrl.irq_buf(interrupt_mtime_irq_c) <= csr.mie_mtie and (trap_ctrl.irq_buf(interrupt_mtime_irq_c) or mtime_irq_i) and (not (trap_ctrl.irq_ack(interrupt_mtime_irq_c) or csr.mip_clear(interrupt_mtime_irq_c)));
|
-- interrupt buffer: custom fast interrupts
|
-- interrupt buffer: custom fast interrupts
|
trap_ctrl.irq_buf(interrupt_firq_0_c) <= csr.mie_firqe(0) and (trap_ctrl.irq_buf(interrupt_firq_0_c) or firq_i(0)) and (not trap_ctrl.irq_ack(interrupt_firq_0_c));
|
trap_ctrl.irq_buf(interrupt_firq_0_c) <= csr.mie_firqe(0) and (trap_ctrl.irq_buf(interrupt_firq_0_c) or firq_i(0)) and (not (trap_ctrl.irq_ack(interrupt_firq_0_c) or csr.mip_clear(interrupt_firq_0_c)));
|
trap_ctrl.irq_buf(interrupt_firq_1_c) <= csr.mie_firqe(1) and (trap_ctrl.irq_buf(interrupt_firq_1_c) or firq_i(1)) and (not trap_ctrl.irq_ack(interrupt_firq_1_c));
|
trap_ctrl.irq_buf(interrupt_firq_1_c) <= csr.mie_firqe(1) and (trap_ctrl.irq_buf(interrupt_firq_1_c) or firq_i(1)) and (not (trap_ctrl.irq_ack(interrupt_firq_1_c) or csr.mip_clear(interrupt_firq_1_c)));
|
trap_ctrl.irq_buf(interrupt_firq_2_c) <= csr.mie_firqe(2) and (trap_ctrl.irq_buf(interrupt_firq_2_c) or firq_i(2)) and (not trap_ctrl.irq_ack(interrupt_firq_2_c));
|
trap_ctrl.irq_buf(interrupt_firq_2_c) <= csr.mie_firqe(2) and (trap_ctrl.irq_buf(interrupt_firq_2_c) or firq_i(2)) and (not (trap_ctrl.irq_ack(interrupt_firq_2_c) or csr.mip_clear(interrupt_firq_2_c)));
|
trap_ctrl.irq_buf(interrupt_firq_3_c) <= csr.mie_firqe(3) and (trap_ctrl.irq_buf(interrupt_firq_3_c) or firq_i(3)) and (not trap_ctrl.irq_ack(interrupt_firq_3_c));
|
trap_ctrl.irq_buf(interrupt_firq_3_c) <= csr.mie_firqe(3) and (trap_ctrl.irq_buf(interrupt_firq_3_c) or firq_i(3)) and (not (trap_ctrl.irq_ack(interrupt_firq_3_c) or csr.mip_clear(interrupt_firq_3_c)));
|
-- trap control --
|
-- trap control --
|
if (trap_ctrl.env_start = '0') then -- no started trap handler
|
if (trap_ctrl.env_start = '0') then -- no started trap handler
|
if (trap_ctrl.exc_fire = '1') or ((trap_ctrl.irq_fire = '1') and -- exception/IRQ detected!
|
if (trap_ctrl.exc_fire = '1') or ((trap_ctrl.irq_fire = '1') and -- exception/IRQ detected!
|
((execute_engine.state = EXECUTE) or (execute_engine.state = TRAP))) then -- sample IRQs in EXECUTE or TRAP state only to continue execution even if permanent IRQ
|
((execute_engine.state = EXECUTE) or (execute_engine.state = TRAP))) then -- sample IRQs in EXECUTE or TRAP state only to continue execution even if permanent IRQ
|
trap_ctrl.cause <= trap_ctrl.cause_nxt; -- capture source ID for program (for mcause csr)
|
trap_ctrl.cause <= trap_ctrl.cause_nxt; -- capture source ID for program (for mcause csr)
|
| Line 1416... |
Line 1406... |
|
|
-- any exception/interrupt? --
|
-- any exception/interrupt? --
|
trap_ctrl.exc_fire <= or_all_f(trap_ctrl.exc_buf); -- exceptions/faults CANNOT be masked
|
trap_ctrl.exc_fire <= or_all_f(trap_ctrl.exc_buf); -- exceptions/faults CANNOT be masked
|
trap_ctrl.irq_fire <= or_all_f(trap_ctrl.irq_buf) and csr.mstatus_mie; -- interrupts CAN be masked
|
trap_ctrl.irq_fire <= or_all_f(trap_ctrl.irq_buf) and csr.mstatus_mie; -- interrupts CAN be masked
|
|
|
|
-- current pending interrupts (for CSR.MIP register) --
|
|
csr.mip_status <= trap_ctrl.irq_buf;
|
|
|
|
|
-- Trap Priority Detector -----------------------------------------------------------------
|
-- Trap Priority Detector -----------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
trap_priority: process(trap_ctrl)
|
trap_priority: process(trap_ctrl)
|
begin
|
begin
|
| Line 1433... |
Line 1426... |
-- interrupt: 1.11 machine external interrupt --
|
-- interrupt: 1.11 machine external interrupt --
|
if (trap_ctrl.irq_buf(interrupt_mext_irq_c) = '1') then
|
if (trap_ctrl.irq_buf(interrupt_mext_irq_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_mei_c;
|
trap_ctrl.cause_nxt <= trap_mei_c;
|
trap_ctrl.irq_ack_nxt(interrupt_mext_irq_c) <= '1';
|
trap_ctrl.irq_ack_nxt(interrupt_mext_irq_c) <= '1';
|
|
|
-- interrupt: 1.7 machine timer interrupt --
|
|
elsif (trap_ctrl.irq_buf(interrupt_mtime_irq_c) = '1') then
|
|
trap_ctrl.cause_nxt <= trap_mti_c;
|
|
trap_ctrl.irq_ack_nxt(interrupt_mtime_irq_c) <= '1';
|
|
|
|
-- interrupt: 1.3 machine SW interrupt --
|
-- interrupt: 1.3 machine SW interrupt --
|
elsif (trap_ctrl.irq_buf(interrupt_msw_irq_c) = '1') then
|
elsif (trap_ctrl.irq_buf(interrupt_msw_irq_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_msi_c;
|
trap_ctrl.cause_nxt <= trap_msi_c;
|
trap_ctrl.irq_ack_nxt(interrupt_msw_irq_c) <= '1';
|
trap_ctrl.irq_ack_nxt(interrupt_msw_irq_c) <= '1';
|
|
|
|
-- interrupt: 1.7 machine timer interrupt --
|
|
elsif (trap_ctrl.irq_buf(interrupt_mtime_irq_c) = '1') then
|
|
trap_ctrl.cause_nxt <= trap_mti_c;
|
|
trap_ctrl.irq_ack_nxt(interrupt_mtime_irq_c) <= '1';
|
|
|
|
|
-- interrupt: 1.16 fast interrupt channel 0 --
|
-- interrupt: 1.16 fast interrupt channel 0 --
|
elsif (trap_ctrl.irq_buf(interrupt_firq_0_c) = '1') then
|
elsif (trap_ctrl.irq_buf(interrupt_firq_0_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_firq0_c;
|
trap_ctrl.cause_nxt <= trap_firq0_c;
|
trap_ctrl.irq_ack_nxt(interrupt_firq_0_c) <= '1';
|
trap_ctrl.irq_ack_nxt(interrupt_firq_0_c) <= '1';
|
| Line 1486... |
Line 1479... |
|
|
-- exception: 0.11 environment call from M-mode --
|
-- exception: 0.11 environment call from M-mode --
|
elsif (trap_ctrl.exc_buf(exception_m_envcall_c) = '1') then
|
elsif (trap_ctrl.exc_buf(exception_m_envcall_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_menv_c;
|
trap_ctrl.cause_nxt <= trap_menv_c;
|
|
|
|
-- exception: 0.8 environment call from U-mode --
|
|
elsif (trap_ctrl.exc_buf(exception_u_envcall_c) = '1') then
|
|
trap_ctrl.cause_nxt <= trap_uenv_c;
|
|
|
-- exception: 0.3 breakpoint --
|
-- exception: 0.3 breakpoint --
|
elsif (trap_ctrl.exc_buf(exception_break_c) = '1') then
|
elsif (trap_ctrl.exc_buf(exception_break_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_brk_c;
|
trap_ctrl.cause_nxt <= trap_brk_c;
|
|
|
|
|
| Line 1525... |
Line 1522... |
atomic_ctrl.lock <= '0';
|
atomic_ctrl.lock <= '0';
|
atomic_ctrl.env_end_ff <= '0';
|
atomic_ctrl.env_end_ff <= '0';
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
if (CPU_EXTENSION_RISCV_A = true) then
|
if (CPU_EXTENSION_RISCV_A = true) then
|
if (atomic_ctrl.env_end_ff = '1') or -- normal termination
|
if (atomic_ctrl.env_end_ff = '1') or -- normal termination
|
(atomic_ctrl.env_abort = '1') or -- fast temrination (error)
|
(atomic_ctrl.env_abort = '1') or -- fast termination (error)
|
(trap_ctrl.env_start = '1') then -- triggered trap -> failure
|
(trap_ctrl.env_start = '1') then -- triggered trap -> failure
|
atomic_ctrl.lock <= '0';
|
atomic_ctrl.lock <= '0';
|
elsif (atomic_ctrl.env_start = '1') then
|
elsif (atomic_ctrl.env_start = '1') then
|
atomic_ctrl.lock <= '1';
|
atomic_ctrl.lock <= '1';
|
end if;
|
end if;
|
| Line 1556... |
Line 1553... |
csr_operand_v := (others => '0');
|
csr_operand_v := (others => '0');
|
csr_operand_v(4 downto 0) := execute_engine.i_reg(19 downto 15); -- uimm5
|
csr_operand_v(4 downto 0) := execute_engine.i_reg(19 downto 15); -- uimm5
|
else -- register
|
else -- register
|
csr_operand_v := rs1_i;
|
csr_operand_v := rs1_i;
|
end if;
|
end if;
|
-- tiny ALU for CSR access operations --
|
-- tiny ALU for CSR write operations --
|
case execute_engine.i_reg(instr_funct3_lsb_c+1 downto instr_funct3_lsb_c) is
|
case execute_engine.i_reg(instr_funct3_lsb_c+1 downto instr_funct3_lsb_c) is
|
when "10" => csr.wdata <= csr.rdata or csr_operand_v; -- CSRRS(I)
|
when "10" => csr.wdata <= csr.rdata or csr_operand_v; -- CSRRS(I)
|
when "11" => csr.wdata <= csr.rdata and (not csr_operand_v); -- CSRRC(I)
|
when "11" => csr.wdata <= csr.rdata and (not csr_operand_v); -- CSRRC(I)
|
when others => csr.wdata <= csr_operand_v; -- CSRRW(I)
|
when others => csr.wdata <= csr_operand_v; -- CSRRW(I)
|
end case;
|
end case;
|
| Line 1583... |
Line 1580... |
csr.mie_mtie <= '0';
|
csr.mie_mtie <= '0';
|
csr.mie_firqe <= (others => '0');
|
csr.mie_firqe <= (others => '0');
|
csr.mtvec <= (others => '0');
|
csr.mtvec <= (others => '0');
|
csr.mscratch <= x"19880704"; -- :)
|
csr.mscratch <= x"19880704"; -- :)
|
csr.mepc <= (others => '0');
|
csr.mepc <= (others => '0');
|
|
-- mcause = TRAP_CODE_RESET (hardware reset, 0x80000000)
|
csr.mcause <= (others => '0');
|
csr.mcause <= (others => '0');
|
|
csr.mcause(csr.mcause'left) <= trap_reset_c(trap_reset_c'left);
|
|
csr.mcause(trap_reset_c'left-1 downto 0) <= trap_reset_c(trap_reset_c'left-1 downto 0);
|
|
--
|
csr.mtval <= (others => '0');
|
csr.mtval <= (others => '0');
|
|
csr.mip_clear <= (others => '0');
|
csr.pmpcfg <= (others => (others => '0'));
|
csr.pmpcfg <= (others => (others => '0'));
|
csr.pmpaddr <= (others => (others => '0'));
|
csr.pmpaddr <= (others => (others => '1'));
|
--
|
--
|
csr.mcycle <= (others => '0');
|
csr.mcycle <= (others => '0');
|
csr.minstret <= (others => '0');
|
csr.minstret <= (others => '0');
|
csr.mcycleh <= (others => '0');
|
csr.mcycleh <= (others => '0');
|
csr.minstreth <= (others => '0');
|
csr.minstreth <= (others => '0');
|
| Line 1599... |
Line 1601... |
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
-- write access? --
|
-- write access? --
|
csr.we <= csr.we_nxt;
|
csr.we <= csr.we_nxt;
|
if (CPU_EXTENSION_RISCV_Zicsr = true) then
|
if (CPU_EXTENSION_RISCV_Zicsr = true) then
|
|
|
|
-- defaults --
|
|
csr.mip_clear <= (others => '0');
|
|
|
-- --------------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------------
|
-- CSR access by application software
|
-- CSR access by application software
|
-- --------------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------------
|
if (csr.we = '1') then -- manual update
|
if (csr.we = '1') then -- manual update
|
case execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) is
|
case execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) is
|
| Line 1613... |
Line 1618... |
csr.mstatus_mie <= csr.wdata(03);
|
csr.mstatus_mie <= csr.wdata(03);
|
csr.mstatus_mpie <= csr.wdata(07);
|
csr.mstatus_mpie <= csr.wdata(07);
|
if (CPU_EXTENSION_RISCV_U = true) then -- user mode implemented
|
if (CPU_EXTENSION_RISCV_U = true) then -- user mode implemented
|
csr.mstatus_mpp(0) <= csr.wdata(11) or csr.wdata(12);
|
csr.mstatus_mpp(0) <= csr.wdata(11) or csr.wdata(12);
|
csr.mstatus_mpp(1) <= csr.wdata(11) or csr.wdata(12);
|
csr.mstatus_mpp(1) <= csr.wdata(11) or csr.wdata(12);
|
|
else -- only machine mode is available
|
|
csr.mstatus_mpp <= priv_mode_m_c;
|
end if;
|
end if;
|
when csr_mie_c => -- R/W: mie - machine interrupt-enable register
|
when csr_mie_c => -- R/W: mie - machine interrupt-enable register
|
csr.mie_msie <= csr.wdata(03); -- machine SW IRQ enable
|
csr.mie_msie <= csr.wdata(03); -- machine SW IRQ enable
|
csr.mie_mtie <= csr.wdata(07); -- machine TIMER IRQ enable
|
csr.mie_mtie <= csr.wdata(07); -- machine TIMER IRQ enable
|
csr.mie_meie <= csr.wdata(11); -- machine EXT IRQ enable
|
csr.mie_meie <= csr.wdata(11); -- machine EXT IRQ enable
|
| Line 1636... |
Line 1643... |
csr.mepc <= csr.wdata(data_width_c-1 downto 1) & '0';
|
csr.mepc <= csr.wdata(data_width_c-1 downto 1) & '0';
|
when csr_mcause_c => -- R/W: mcause - machine trap cause
|
when csr_mcause_c => -- R/W: mcause - machine trap cause
|
csr.mcause <= (others => '0');
|
csr.mcause <= (others => '0');
|
csr.mcause(csr.mcause'left) <= csr.wdata(31); -- 1: interrupt, 0: exception
|
csr.mcause(csr.mcause'left) <= csr.wdata(31); -- 1: interrupt, 0: exception
|
csr.mcause(4 downto 0) <= csr.wdata(4 downto 0); -- identifier
|
csr.mcause(4 downto 0) <= csr.wdata(4 downto 0); -- identifier
|
when csr_mtval_c => -- R/W: mtval - machine bad address or instruction
|
when csr_mtval_c => -- R/W: mtval - machine bad address/instruction
|
csr.mtval <= csr.wdata;
|
csr.mtval <= csr.wdata;
|
|
when csr_mip_c => -- R/W: mip - machine interrupt pending
|
|
csr.mip_clear(interrupt_msw_irq_c) <= not csr.wdata(03);
|
|
csr.mip_clear(interrupt_mtime_irq_c) <= not csr.wdata(07);
|
|
csr.mip_clear(interrupt_mext_irq_c) <= not csr.wdata(11);
|
|
--
|
|
csr.mip_clear(interrupt_firq_0_c) <= not csr.wdata(16);
|
|
csr.mip_clear(interrupt_firq_1_c) <= not csr.wdata(17);
|
|
csr.mip_clear(interrupt_firq_2_c) <= not csr.wdata(18);
|
|
csr.mip_clear(interrupt_firq_3_c) <= not csr.wdata(19);
|
|
|
-- physical memory protection - configuration --
|
-- physical memory protection - configuration --
|
-- --------------------------------------------------------------------
|
-- --------------------------------------------------------------------
|
when csr_pmpcfg0_c => -- R/W: pmpcfg0 - PMP configuration register 0
|
when csr_pmpcfg0_c => -- R/W: pmpcfg0 - PMP configuration register 0
|
if (PMP_USE = true) and (PMP_NUM_REGIONS >= 1) then
|
if (PMP_USE = true) and (pmp_num_regions_c >= 1) then
|
for j in 0 to 3 loop -- bytes in pmpcfg CSR
|
for j in 0 to 3 loop -- bytes in pmpcfg CSR
|
if ((j+1) <= PMP_NUM_REGIONS) then
|
if ((j+1) <= pmp_num_regions_c) then
|
if (csr.pmpcfg(0+j)(7) = '0') then -- unlocked pmpcfg access
|
if (csr.pmpcfg(0+j)(7) = '0') then -- unlocked pmpcfg access
|
csr.pmpcfg(0+j)(0) <= csr.wdata(j*8+0); -- R (rights.read)
|
csr.pmpcfg(0+j)(0) <= csr.wdata(j*8+0); -- R (rights.read)
|
csr.pmpcfg(0+j)(1) <= csr.wdata(j*8+1); -- W (rights.write)
|
csr.pmpcfg(0+j)(1) <= csr.wdata(j*8+1); -- W (rights.write)
|
csr.pmpcfg(0+j)(2) <= csr.wdata(j*8+2); -- X (rights.execute)
|
csr.pmpcfg(0+j)(2) <= csr.wdata(j*8+2); -- X (rights.execute)
|
csr.pmpcfg(0+j)(3) <= csr.wdata(j*8+3) and csr.wdata(j*8+4); -- A_L
|
csr.pmpcfg(0+j)(3) <= csr.wdata(j*8+3) and csr.wdata(j*8+4); -- A_L
|
| Line 1659... |
Line 1675... |
end if;
|
end if;
|
end if;
|
end if;
|
end loop; -- j (bytes in CSR)
|
end loop; -- j (bytes in CSR)
|
end if;
|
end if;
|
when csr_pmpcfg1_c => -- R/W: pmpcfg1 - PMP configuration register 1
|
when csr_pmpcfg1_c => -- R/W: pmpcfg1 - PMP configuration register 1
|
if (PMP_USE = true) and (PMP_NUM_REGIONS >= 5) then
|
if (PMP_USE = true) and (pmp_num_regions_c >= 5) then
|
for j in 0 to 3 loop -- bytes in pmpcfg CSR
|
for j in 0 to 3 loop -- bytes in pmpcfg CSR
|
if ((j+1+4) <= PMP_NUM_REGIONS) then
|
if ((j+1+4) <= pmp_num_regions_c) then
|
if (csr.pmpcfg(4+j)(7) = '0') then -- unlocked pmpcfg access
|
if (csr.pmpcfg(4+j)(7) = '0') then -- unlocked pmpcfg access
|
csr.pmpcfg(4+j)(0) <= csr.wdata(j*8+0); -- R (rights.read)
|
csr.pmpcfg(4+j)(0) <= csr.wdata(j*8+0); -- R (rights.read)
|
csr.pmpcfg(4+j)(1) <= csr.wdata(j*8+1); -- W (rights.write)
|
csr.pmpcfg(4+j)(1) <= csr.wdata(j*8+1); -- W (rights.write)
|
csr.pmpcfg(4+j)(2) <= csr.wdata(j*8+2); -- X (rights.execute)
|
csr.pmpcfg(4+j)(2) <= csr.wdata(j*8+2); -- X (rights.execute)
|
csr.pmpcfg(4+j)(3) <= csr.wdata(j*8+3) and csr.wdata(j*8+4); -- A_L
|
csr.pmpcfg(4+j)(3) <= csr.wdata(j*8+3) and csr.wdata(j*8+4); -- A_L
|
| Line 1681... |
Line 1697... |
-- physical memory protection - addresses --
|
-- physical memory protection - addresses --
|
-- --------------------------------------------------------------------
|
-- --------------------------------------------------------------------
|
when csr_pmpaddr0_c | csr_pmpaddr1_c | csr_pmpaddr2_c | csr_pmpaddr3_c |
|
when csr_pmpaddr0_c | csr_pmpaddr1_c | csr_pmpaddr2_c | csr_pmpaddr3_c |
|
csr_pmpaddr4_c | csr_pmpaddr5_c | csr_pmpaddr6_c | csr_pmpaddr7_c => -- R/W: pmpaddr0..7 - PMP address register 0..7
|
csr_pmpaddr4_c | csr_pmpaddr5_c | csr_pmpaddr6_c | csr_pmpaddr7_c => -- R/W: pmpaddr0..7 - PMP address register 0..7
|
if (PMP_USE = true) then
|
if (PMP_USE = true) then
|
for i in 0 to PMP_NUM_REGIONS-1 loop
|
for i in 0 to pmp_num_regions_c-1 loop
|
if (execute_engine.i_reg(23 downto 20) = std_ulogic_vector(to_unsigned(i, 4))) and (csr.pmpcfg(i)(7) = '0') then -- unlocked pmpaddr access
|
if (execute_engine.i_reg(23 downto 20) = std_ulogic_vector(to_unsigned(i, 4))) and (csr.pmpcfg(i)(7) = '0') then -- unlocked pmpaddr access
|
csr.pmpaddr(i) <= csr.wdata(31 downto 1) & '0'; -- min granularity is 8 bytes -> bit zero cannot be configured
|
csr.pmpaddr(i) <= csr.wdata;
|
|
csr.pmpaddr(i)(index_size_f(pmp_min_granularity_c)-4 downto 0) <= (others => '1');
|
end if;
|
end if;
|
end loop; -- i (CSRs)
|
end loop; -- i (CSRs)
|
end if;
|
end if;
|
|
|
-- undefined --
|
-- undefined --
|
| Line 1700... |
Line 1717... |
-- --------------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------------
|
-- CSR access by hardware
|
-- CSR access by hardware
|
-- --------------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------------
|
else
|
else
|
|
|
-- mepc & mtval: machine exception PC & machine trap value register --
|
-- mcause, mepc, mtval: machine trap cause, PC and value register --
|
-- --------------------------------------------------------------------
|
-- --------------------------------------------------------------------
|
if (trap_ctrl.env_start_ack = '1') then -- trap handler starting?
|
if (trap_ctrl.env_start_ack = '1') then -- trap handler starting?
|
|
-- trap cause ID code --
|
|
csr.mcause <= (others => '0');
|
|
csr.mcause(csr.mcause'left) <= trap_ctrl.cause(trap_ctrl.cause'left); -- 1: interrupt, 0: exception
|
|
csr.mcause(4 downto 0) <= trap_ctrl.cause(4 downto 0); -- identifier
|
|
-- trap PC --
|
if (trap_ctrl.cause(trap_ctrl.cause'left) = '1') then -- for INTERRUPTS
|
if (trap_ctrl.cause(trap_ctrl.cause'left) = '1') then -- for INTERRUPTS
|
csr.mepc <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- this is the CURRENT pc = interrupted instruction
|
csr.mepc <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- this is the CURRENT pc = interrupted instruction
|
csr.mtval <= (others => '0'); -- mtval is zero for interrupts
|
else -- for EXCEPTIONS
|
else -- for EXCEPTIONS (according to their priority)
|
|
csr.mepc <= execute_engine.last_pc(data_width_c-1 downto 1) & '0'; -- this is the LAST pc = last executed instruction
|
csr.mepc <= execute_engine.last_pc(data_width_c-1 downto 1) & '0'; -- this is the LAST pc = last executed instruction
|
if (trap_ctrl.cause(4 downto 0) = trap_iba_c(4 downto 0)) or -- instruction access error OR
|
end if;
|
(trap_ctrl.cause(4 downto 0) = trap_ima_c(4 downto 0)) or -- misaligned instruction address OR
|
-- trap value --
|
(trap_ctrl.cause(4 downto 0) = trap_brk_c(4 downto 0)) or -- breakpoint OR
|
case trap_ctrl.cause is
|
(trap_ctrl.cause(4 downto 0) = trap_menv_c(4 downto 0)) then -- environment call
|
when trap_ima_c | trap_iba_c => -- misaligned instruction address OR instruction access error
|
csr.mtval <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- address of faulting instruction
|
csr.mtval <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- address of faulting instruction
|
elsif (trap_ctrl.cause(4 downto 0) = trap_iil_c(4 downto 0)) then -- illegal instruction
|
when trap_brk_c => -- breakpoint
|
csr.mtval <= execute_engine.i_reg_last; -- faulting instruction itself
|
csr.mtval <= execute_engine.last_pc(data_width_c-1 downto 1) & '0'; -- address of breakpoint instruction
|
else -- load/store misalignments/access errors
|
when trap_lma_c | trap_lbe_c | trap_sma_c | trap_sbe_c => -- misaligned load/store address OR load/store access error
|
csr.mtval <= mar_i; -- faulting data access address
|
csr.mtval <= mar_i; -- faulting data access address
|
end if;
|
when trap_iil_c => -- illegal instruction
|
end if;
|
csr.mtval <= execute_engine.i_reg_last; -- faulting instruction itself
|
|
when others => -- everything else including interrupts
|
|
csr.mtval <= (others => '0');
|
|
end case;
|
end if;
|
end if;
|
|
|
-- mstatus: context switch --
|
-- mstatus: context switch --
|
-- --------------------------------------------------------------------
|
-- --------------------------------------------------------------------
|
if (trap_ctrl.env_start_ack = '1') then -- ENTER: trap handler starting?
|
if (trap_ctrl.env_start_ack = '1') then -- ENTER: trap handler starting?
|
-- trap ID code --
|
|
csr.mcause <= (others => '0');
|
|
csr.mcause(csr.mcause'left) <= trap_ctrl.cause(trap_ctrl.cause'left); -- 1: interrupt, 0: exception
|
|
csr.mcause(4 downto 0) <= trap_ctrl.cause(4 downto 0); -- identifier
|
|
--
|
|
csr.mstatus_mie <= '0'; -- disable interrupts
|
csr.mstatus_mie <= '0'; -- disable interrupts
|
csr.mstatus_mpie <= csr.mstatus_mie; -- buffer previous mie state
|
csr.mstatus_mpie <= csr.mstatus_mie; -- buffer previous mie state
|
if (CPU_EXTENSION_RISCV_U = true) then -- implement user mode
|
if (CPU_EXTENSION_RISCV_U = true) then -- implement user mode
|
csr.privilege <= priv_mode_m_c; -- execute trap in machine mode
|
csr.privilege <= priv_mode_m_c; -- execute trap in machine mode
|
csr.mstatus_mpp <= csr.privilege; -- buffer previous privilege mode
|
csr.mstatus_mpp <= csr.privilege; -- buffer previous privilege mode
|
| Line 1740... |
Line 1759... |
elsif (trap_ctrl.env_end = '1') then -- EXIT: return from exception
|
elsif (trap_ctrl.env_end = '1') then -- EXIT: return from exception
|
csr.mstatus_mie <= csr.mstatus_mpie; -- restore global IRQ enable flag
|
csr.mstatus_mie <= csr.mstatus_mpie; -- restore global IRQ enable flag
|
csr.mstatus_mpie <= '1';
|
csr.mstatus_mpie <= '1';
|
if (CPU_EXTENSION_RISCV_U = true) then -- implement user mode
|
if (CPU_EXTENSION_RISCV_U = true) then -- implement user mode
|
csr.privilege <= csr.mstatus_mpp; -- go back to previous privilege mode
|
csr.privilege <= csr.mstatus_mpp; -- go back to previous privilege mode
|
csr.mstatus_mpp <= priv_mode_u_c;
|
csr.mstatus_mpp <= priv_mode_m_c;
|
end if;
|
end if;
|
end if;
|
end if;
|
-- user mode NOT implemented --
|
-- user mode NOT implemented --
|
if (CPU_EXTENSION_RISCV_U = false) then
|
if (CPU_EXTENSION_RISCV_U = false) then
|
csr.privilege <= priv_mode_m_c;
|
csr.privilege <= priv_mode_m_c;
|
| Line 1752... |
Line 1771... |
end if;
|
end if;
|
|
|
end if; -- hardware csr access
|
end if; -- hardware csr access
|
|
|
-- --------------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------------
|
-- Counter CSRs
|
-- Counter CSRs (each counter is split in 2 32-bit counters)
|
-- --------------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------------
|
|
if (zicnt_en_c = true) then -- implement standard RISC-V performance counters?
|
-- mcycle (cycle) --
|
-- [m]cycle --
|
if (csr.we = '1') and (execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) = csr_mcycle_c) then -- write access
|
if (csr.we = '1') and (execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) = csr_mcycle_c) then -- write access
|
csr.mcycle <= '0' & csr.wdata;
|
csr.mcycle <= '0' & csr.wdata;
|
mcycle_msb <= '0';
|
mcycle_msb <= '0';
|
elsif (execute_engine.sleep = '0') then -- automatic update (if CPU is not in sleep mode)
|
elsif (execute_engine.sleep = '0') then -- automatic update (if CPU is not in sleep mode)
|
csr.mcycle <= std_ulogic_vector(unsigned(csr.mcycle) + 1);
|
csr.mcycle <= std_ulogic_vector(unsigned(csr.mcycle) + 1);
|
mcycle_msb <= csr.mcycle(csr.mcycle'left);
|
mcycle_msb <= csr.mcycle(csr.mcycle'left);
|
end if;
|
end if;
|
|
|
-- mcycleh (cycleh) --
|
-- [m]cycleh --
|
if (csr.we = '1') and (execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) = csr_mcycleh_c) then -- write access
|
if (csr.we = '1') and (execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) = csr_mcycleh_c) then -- write access
|
csr.mcycleh <= csr.wdata(csr.mcycleh'left downto 0);
|
csr.mcycleh <= csr.wdata(csr.mcycleh'left downto 0);
|
elsif ((mcycle_msb xor csr.mcycle(csr.mcycle'left)) = '1') then -- automatic update
|
elsif ((mcycle_msb xor csr.mcycle(csr.mcycle'left)) = '1') then -- automatic update
|
csr.mcycleh <= std_ulogic_vector(unsigned(csr.mcycleh) + 1);
|
csr.mcycleh <= std_ulogic_vector(unsigned(csr.mcycleh) + 1);
|
end if;
|
end if;
|
|
|
-- minstret (instret) --
|
-- [m]instret --
|
if (csr.we = '1') and (execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) = csr_minstret_c) then -- write access
|
if (csr.we = '1') and (execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) = csr_minstret_c) then -- write access
|
csr.minstret <= '0' & csr.wdata;
|
csr.minstret <= '0' & csr.wdata;
|
minstret_msb <= '0';
|
minstret_msb <= '0';
|
elsif (execute_engine.state_prev /= EXECUTE) and (execute_engine.state = EXECUTE) then -- automatic update (if CPU commits an instruction)
|
elsif (execute_engine.state = EXECUTE) then -- automatic update (if CPU actually executes an instruction)
|
csr.minstret <= std_ulogic_vector(unsigned(csr.minstret) + 1);
|
csr.minstret <= std_ulogic_vector(unsigned(csr.minstret) + 1);
|
minstret_msb <= csr.minstret(csr.minstret'left);
|
minstret_msb <= csr.minstret(csr.minstret'left);
|
end if;
|
end if;
|
|
|
-- minstreth (instreth) --
|
-- [m]instreth --
|
if (csr.we = '1') and (execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) = csr_minstreth_c) then -- write access
|
if (csr.we = '1') and (execute_engine.i_reg(instr_csr_id_msb_c downto instr_csr_id_lsb_c) = csr_minstreth_c) then -- write access
|
csr.minstreth <= csr.wdata(csr.minstreth'left downto 0);
|
csr.minstreth <= csr.wdata(csr.minstreth'left downto 0);
|
elsif ((minstret_msb xor csr.minstret(csr.minstret'left)) = '1') then -- automatic update
|
elsif ((minstret_msb xor csr.minstret(csr.minstret'left)) = '1') then -- automatic update
|
csr.minstreth <= std_ulogic_vector(unsigned(csr.minstreth) + 1);
|
csr.minstreth <= std_ulogic_vector(unsigned(csr.minstreth) + 1);
|
end if;
|
end if;
|
|
else -- performance counters NOT implemented (not RISC-V-compliant!)
|
|
csr.mcycle <= (others => '0');
|
|
csr.minstret <= (others => '0');
|
|
csr.mcycleh <= (others => '0');
|
|
csr.minstreth <= (others => '0');
|
|
mcycle_msb <= '0';
|
|
minstret_msb <= '0';
|
|
end if;
|
|
|
end if;
|
end if;
|
end if;
|
end if;
|
end process csr_write_access;
|
end process csr_write_access;
|
|
|
|
-- decode privilege mode --
|
|
csr.priv_m_mode <= '1' when (csr.privilege = priv_mode_m_c) or (CPU_EXTENSION_RISCV_U = false) else '0';
|
|
csr.priv_u_mode <= '1' when (csr.privilege = priv_mode_u_c) and (CPU_EXTENSION_RISCV_U = true) else '0';
|
|
|
-- PMP configuration output to bus unit --
|
-- PMP configuration output to bus unit --
|
pmp_output: process(csr)
|
pmp_output: process(csr)
|
begin
|
begin
|
pmp_addr_o <= (others => (others => '0'));
|
pmp_addr_o <= (others => (others => '0'));
|
pmp_ctrl_o <= (others => (others => '0'));
|
pmp_ctrl_o <= (others => (others => '0'));
|
if (PMP_USE = true) then
|
if (PMP_USE = true) then
|
for i in 0 to PMP_NUM_REGIONS-1 loop
|
for i in 0 to pmp_num_regions_c-1 loop
|
pmp_addr_o(i) <= csr.pmpaddr(i) & "00";
|
pmp_addr_o(i) <= csr.pmpaddr(i) & "11";
|
|
pmp_addr_o(i)(index_size_f(pmp_min_granularity_c)-4 downto 0) <= (others => '1');
|
pmp_ctrl_o(i) <= csr.pmpcfg(i);
|
pmp_ctrl_o(i) <= csr.pmpcfg(i);
|
end loop; -- i
|
end loop; -- i
|
end if;
|
end if;
|
end process pmp_output;
|
end process pmp_output;
|
|
|
| Line 1821... |
Line 1853... |
when csr_mstatus_c => -- R/W: mstatus - machine status register
|
when csr_mstatus_c => -- R/W: mstatus - machine status register
|
csr.rdata(03) <= csr.mstatus_mie; -- MIE
|
csr.rdata(03) <= csr.mstatus_mie; -- MIE
|
csr.rdata(07) <= csr.mstatus_mpie; -- MPIE
|
csr.rdata(07) <= csr.mstatus_mpie; -- MPIE
|
csr.rdata(11) <= csr.mstatus_mpp(0); -- MPP: machine previous privilege mode low
|
csr.rdata(11) <= csr.mstatus_mpp(0); -- MPP: machine previous privilege mode low
|
csr.rdata(12) <= csr.mstatus_mpp(1); -- MPP: machine previous privilege mode high
|
csr.rdata(12) <= csr.mstatus_mpp(1); -- MPP: machine previous privilege mode high
|
|
when csr_mstatush_c => -- R/-: mstatush - machine status register - high part
|
|
csr.rdata(05) <= '1'; -- MBE: CPU/Processor is BIG-ENDIAN
|
when csr_misa_c => -- R/-: misa - ISA and extensions
|
when csr_misa_c => -- R/-: misa - ISA and extensions
|
csr.rdata(00) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_A); -- A CPU extension
|
csr.rdata(00) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_A); -- A CPU extension
|
csr.rdata(02) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_C); -- C CPU extension
|
csr.rdata(02) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_C); -- C CPU extension
|
csr.rdata(04) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- E CPU extension
|
csr.rdata(04) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- E CPU extension
|
csr.rdata(08) <= not bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- I CPU extension (if not E)
|
csr.rdata(08) <= not bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- I CPU extension (if not E)
|
| Line 1853... |
Line 1887... |
when csr_mcause_c => -- R/W: mcause - machine trap cause
|
when csr_mcause_c => -- R/W: mcause - machine trap cause
|
csr.rdata <= csr.mcause;
|
csr.rdata <= csr.mcause;
|
when csr_mtval_c => -- R/W: mtval - machine bad address or instruction
|
when csr_mtval_c => -- R/W: mtval - machine bad address or instruction
|
csr.rdata <= csr.mtval;
|
csr.rdata <= csr.mtval;
|
when csr_mip_c => -- R/W: mip - machine interrupt pending
|
when csr_mip_c => -- R/W: mip - machine interrupt pending
|
csr.rdata(03) <= trap_ctrl.irq_buf(interrupt_msw_irq_c);
|
csr.rdata(03) <= csr.mip_status(interrupt_msw_irq_c);
|
csr.rdata(07) <= trap_ctrl.irq_buf(interrupt_mtime_irq_c);
|
csr.rdata(07) <= csr.mip_status(interrupt_mtime_irq_c);
|
csr.rdata(11) <= trap_ctrl.irq_buf(interrupt_mext_irq_c);
|
csr.rdata(11) <= csr.mip_status(interrupt_mext_irq_c);
|
--
|
--
|
csr.rdata(16) <= trap_ctrl.irq_buf(interrupt_firq_0_c);
|
csr.rdata(16) <= csr.mip_status(interrupt_firq_0_c);
|
csr.rdata(17) <= trap_ctrl.irq_buf(interrupt_firq_1_c);
|
csr.rdata(17) <= csr.mip_status(interrupt_firq_1_c);
|
csr.rdata(18) <= trap_ctrl.irq_buf(interrupt_firq_2_c);
|
csr.rdata(18) <= csr.mip_status(interrupt_firq_2_c);
|
csr.rdata(19) <= trap_ctrl.irq_buf(interrupt_firq_3_c);
|
csr.rdata(19) <= csr.mip_status(interrupt_firq_3_c);
|
|
|
-- physical memory protection - configuration --
|
-- physical memory protection - configuration --
|
when csr_pmpcfg0_c => -- R/W: pmpcfg0 - physical memory protection configuration register 0
|
when csr_pmpcfg0_c => -- R/W: pmpcfg0 - physical memory protection configuration register 0
|
if (PMP_USE = true) then
|
if (PMP_USE = true) then
|
if (PMP_NUM_REGIONS >= 1) then
|
if (pmp_num_regions_c >= 1) then
|
csr.rdata(07 downto 00) <= csr.pmpcfg(0);
|
csr.rdata(07 downto 00) <= csr.pmpcfg(0);
|
end if;
|
end if;
|
if (PMP_NUM_REGIONS >= 2) then
|
if (pmp_num_regions_c >= 2) then
|
csr.rdata(15 downto 08) <= csr.pmpcfg(1);
|
csr.rdata(15 downto 08) <= csr.pmpcfg(1);
|
end if;
|
end if;
|
if (PMP_NUM_REGIONS >= 3) then
|
if (pmp_num_regions_c >= 3) then
|
csr.rdata(23 downto 16) <= csr.pmpcfg(2);
|
csr.rdata(23 downto 16) <= csr.pmpcfg(2);
|
end if;
|
end if;
|
if (PMP_NUM_REGIONS >= 4) then
|
if (pmp_num_regions_c >= 4) then
|
csr.rdata(31 downto 24) <= csr.pmpcfg(3);
|
csr.rdata(31 downto 24) <= csr.pmpcfg(3);
|
end if;
|
end if;
|
end if;
|
end if;
|
when csr_pmpcfg1_c => -- R/W: pmpcfg1 - physical memory protection configuration register 1
|
when csr_pmpcfg1_c => -- R/W: pmpcfg1 - physical memory protection configuration register 1
|
if (PMP_USE = true) then
|
if (PMP_USE = true) then
|
if (PMP_NUM_REGIONS >= 5) then
|
if (pmp_num_regions_c >= 5) then
|
csr.rdata(07 downto 00) <= csr.pmpcfg(4);
|
csr.rdata(07 downto 00) <= csr.pmpcfg(4);
|
end if;
|
end if;
|
if (PMP_NUM_REGIONS >= 6) then
|
if (pmp_num_regions_c >= 6) then
|
csr.rdata(15 downto 08) <= csr.pmpcfg(5);
|
csr.rdata(15 downto 08) <= csr.pmpcfg(5);
|
end if;
|
end if;
|
if (PMP_NUM_REGIONS >= 7) then
|
if (pmp_num_regions_c >= 7) then
|
csr.rdata(23 downto 16) <= csr.pmpcfg(6);
|
csr.rdata(23 downto 16) <= csr.pmpcfg(6);
|
end if;
|
end if;
|
if (PMP_NUM_REGIONS >= 8) then
|
if (pmp_num_regions_c >= 8) then
|
csr.rdata(31 downto 24) <= csr.pmpcfg(7);
|
csr.rdata(31 downto 24) <= csr.pmpcfg(7);
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
-- physical memory protection - addresses --
|
-- physical memory protection - addresses --
|
when csr_pmpaddr0_c => -- R/W: pmpaddr0 - physical memory protection address register 0
|
when csr_pmpaddr0_c => -- R/W: pmpaddr0 - physical memory protection address register 0
|
if (PMP_USE = true) and (PMP_NUM_REGIONS >= 1) then
|
if (PMP_USE = true) and (pmp_num_regions_c >= 1) then
|
csr.rdata <= csr.pmpaddr(0);
|
csr.rdata <= csr.pmpaddr(0);
|
if (csr.pmpcfg(0)(4 downto 3) = "00") then -- mode = off
|
if (csr.pmpcfg(0)(4 downto 3) = "00") then -- mode = off
|
csr.rdata(PMP_GRANULARITY-1 downto 0) <= (others => '0'); -- required for granularity check by SW
|
csr.rdata(index_size_f(pmp_min_granularity_c)-3 downto 0) <= (others => '0'); -- required for granularity check by SW
|
else -- mode = NAPOT
|
|
csr.rdata(PMP_GRANULARITY-2 downto 0) <= (others => '1');
|
|
end if;
|
end if;
|
end if;
|
end if;
|
when csr_pmpaddr1_c => -- R/W: pmpaddr1 - physical memory protection address register 1
|
when csr_pmpaddr1_c => -- R/W: pmpaddr1 - physical memory protection address register 1
|
if (PMP_USE = true) and (PMP_NUM_REGIONS >= 2) then
|
if (PMP_USE = true) and (pmp_num_regions_c >= 2) then
|
csr.rdata <= csr.pmpaddr(1);
|
csr.rdata <= csr.pmpaddr(1);
|
if (csr.pmpcfg(1)(4 downto 3) = "00") then -- mode = off
|
if (csr.pmpcfg(1)(4 downto 3) = "00") then -- mode = off
|
csr.rdata(PMP_GRANULARITY-1 downto 0) <= (others => '0'); -- required for granularity check by SW
|
csr.rdata(index_size_f(pmp_min_granularity_c)-3 downto 0) <= (others => '0'); -- required for granularity check by SW
|
else -- mode = NAPOT
|
|
csr.rdata(PMP_GRANULARITY-2 downto 0) <= (others => '1');
|
|
end if;
|
end if;
|
end if;
|
end if;
|
when csr_pmpaddr2_c => -- R/W: pmpaddr2 - physical memory protection address register 2
|
when csr_pmpaddr2_c => -- R/W: pmpaddr2 - physical memory protection address register 2
|
if (PMP_USE = true) and (PMP_NUM_REGIONS >= 3) then
|
if (PMP_USE = true) and (pmp_num_regions_c >= 3) then
|
csr.rdata <= csr.pmpaddr(2);
|
csr.rdata <= csr.pmpaddr(2);
|
if (csr.pmpcfg(2)(4 downto 3) = "00") then -- mode = off
|
if (csr.pmpcfg(2)(4 downto 3) = "00") then -- mode = off
|
csr.rdata(PMP_GRANULARITY-1 downto 0) <= (others => '0'); -- required for granularity check by SW
|
csr.rdata(index_size_f(pmp_min_granularity_c)-3 downto 0) <= (others => '0'); -- required for granularity check by SW
|
else -- mode = NAPOT
|
|
csr.rdata(PMP_GRANULARITY-2 downto 0) <= (others => '1');
|
|
end if;
|
end if;
|
end if;
|
end if;
|
when csr_pmpaddr3_c => -- R/W: pmpaddr3 - physical memory protection address register 3
|
when csr_pmpaddr3_c => -- R/W: pmpaddr3 - physical memory protection address register 3
|
if (PMP_USE = true) and (PMP_NUM_REGIONS >= 4) then
|
if (PMP_USE = true) and (pmp_num_regions_c >= 4) then
|
csr.rdata <= csr.pmpaddr(3);
|
csr.rdata <= csr.pmpaddr(3);
|
if (csr.pmpcfg(3)(4 downto 3) = "00") then -- mode = off
|
if (csr.pmpcfg(3)(4 downto 3) = "00") then -- mode = off
|
csr.rdata(PMP_GRANULARITY-1 downto 0) <= (others => '0'); -- required for granularity check by SW
|
csr.rdata(index_size_f(pmp_min_granularity_c)-3 downto 0) <= (others => '0'); -- required for granularity check by SW
|
else -- mode = NAPOT
|
|
csr.rdata(PMP_GRANULARITY-2 downto 0) <= (others => '1');
|
|
end if;
|
end if;
|
end if;
|
end if;
|
when csr_pmpaddr4_c => -- R/W: pmpaddr4 - physical memory protection address register 4
|
when csr_pmpaddr4_c => -- R/W: pmpaddr4 - physical memory protection address register 4
|
if (PMP_USE = true) and (PMP_NUM_REGIONS >= 5) then
|
if (PMP_USE = true) and (pmp_num_regions_c >= 5) then
|
csr.rdata <= csr.pmpaddr(4);
|
csr.rdata <= csr.pmpaddr(4);
|
if (csr.pmpcfg(4)(4 downto 3) = "00") then -- mode = off
|
if (csr.pmpcfg(4)(4 downto 3) = "00") then -- mode = off
|
csr.rdata(PMP_GRANULARITY-1 downto 0) <= (others => '0'); -- required for granularity check by SW
|
csr.rdata(index_size_f(pmp_min_granularity_c)-3 downto 0) <= (others => '0'); -- required for granularity check by SW
|
else -- mode = NAPOT
|
|
csr.rdata(PMP_GRANULARITY-2 downto 0) <= (others => '1');
|
|
end if;
|
end if;
|
end if;
|
end if;
|
when csr_pmpaddr5_c => -- R/W: pmpaddr5 - physical memory protection address register 5
|
when csr_pmpaddr5_c => -- R/W: pmpaddr5 - physical memory protection address register 5
|
if (PMP_USE = true) and (PMP_NUM_REGIONS >= 6) then
|
if (PMP_USE = true) and (pmp_num_regions_c >= 6) then
|
csr.rdata <= csr.pmpaddr(5);
|
csr.rdata <= csr.pmpaddr(5);
|
if (csr.pmpcfg(5)(4 downto 3) = "00") then -- mode = off
|
if (csr.pmpcfg(5)(4 downto 3) = "00") then -- mode = off
|
csr.rdata(PMP_GRANULARITY-1 downto 0) <= (others => '0'); -- required for granularity check by SW
|
csr.rdata(index_size_f(pmp_min_granularity_c)-3 downto 0) <= (others => '0'); -- required for granularity check by SW
|
else -- mode = NAPOT
|
|
csr.rdata(PMP_GRANULARITY-2 downto 0) <= (others => '1');
|
|
end if;
|
end if;
|
end if;
|
end if;
|
when csr_pmpaddr6_c => -- R/W: pmpaddr6 - physical memory protection address register 6
|
when csr_pmpaddr6_c => -- R/W: pmpaddr6 - physical memory protection address register 6
|
if (PMP_USE = true) and (PMP_NUM_REGIONS >= 7) then
|
if (PMP_USE = true) and (pmp_num_regions_c >= 7) then
|
csr.rdata <= csr.pmpaddr(6);
|
csr.rdata <= csr.pmpaddr(6);
|
if (csr.pmpcfg(6)(4 downto 3) = "00") then -- mode = off
|
if (csr.pmpcfg(6)(4 downto 3) = "00") then -- mode = off
|
csr.rdata(PMP_GRANULARITY-1 downto 0) <= (others => '0'); -- required for granularity check by SW
|
csr.rdata(index_size_f(pmp_min_granularity_c)-3 downto 0) <= (others => '0'); -- required for granularity check by SW
|
else -- mode = NAPOT
|
|
csr.rdata(PMP_GRANULARITY-2 downto 0) <= (others => '1');
|
|
end if;
|
end if;
|
end if;
|
end if;
|
when csr_pmpaddr7_c => -- R/W: pmpaddr7 - physical memory protection address register 7
|
when csr_pmpaddr7_c => -- R/W: pmpaddr7 - physical memory protection address register 7
|
if (PMP_USE = true) and (PMP_NUM_REGIONS >= 8) then
|
if (PMP_USE = true) and (pmp_num_regions_c >= 8) then
|
csr.rdata <= csr.pmpaddr(7);
|
csr.rdata <= csr.pmpaddr(7);
|
if (csr.pmpcfg(7)(4 downto 3) = "00") then -- mode = off
|
if (csr.pmpcfg(7)(4 downto 3) = "00") then -- mode = off
|
csr.rdata(PMP_GRANULARITY-1 downto 0) <= (others => '0'); -- required for granularity check by SW
|
csr.rdata(index_size_f(pmp_min_granularity_c)-3 downto 0) <= (others => '0'); -- required for granularity check by SW
|
else -- mode = NAPOT
|
|
csr.rdata(PMP_GRANULARITY-2 downto 0) <= (others => '1');
|
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
-- counters and timers --
|
-- counters and timers --
|
when csr_cycle_c | csr_mcycle_c => -- R/(W): [m]cycle: Cycle counter LOW
|
when csr_cycle_c | csr_mcycle_c => -- R/(W): [m]cycle: Cycle counter LOW
|
| Line 1997... |
Line 2015... |
-- custom machine read-only CSRs --
|
-- custom machine read-only CSRs --
|
when csr_mzext_c => -- R/-: mzext - available Z* extensions
|
when csr_mzext_c => -- R/-: mzext - available Z* extensions
|
csr.rdata(0) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr); -- RISC-V.Zicsr CPU extension
|
csr.rdata(0) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr); -- RISC-V.Zicsr CPU extension
|
csr.rdata(1) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- RISC-V.Zifencei CPU extension
|
csr.rdata(1) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- RISC-V.Zifencei CPU extension
|
csr.rdata(2) <= bool_to_ulogic_f(PMP_USE); -- RISC-V physical memory protection
|
csr.rdata(2) <= bool_to_ulogic_f(PMP_USE); -- RISC-V physical memory protection
|
|
csr.rdata(3) <= bool_to_ulogic_f(zicnt_en_c); -- RISC-V performance counters ([m]cycle[h] & [m]instret[h]) implemented
|
|
|
-- undefined/unavailable --
|
-- undefined/unavailable --
|
when others =>
|
when others =>
|
csr.rdata <= (others => '0'); -- not implemented
|
csr.rdata <= (others => '0'); -- not implemented
|
|
|
