| Line 87... |
Line 87... |
-- interrupts (risc-v compliant) --
|
-- interrupts (risc-v compliant) --
|
msw_irq_i : in std_ulogic; -- machine software interrupt
|
msw_irq_i : in std_ulogic; -- machine software interrupt
|
mext_irq_i : in std_ulogic; -- machine external interrupt
|
mext_irq_i : in std_ulogic; -- machine external interrupt
|
mtime_irq_i : in std_ulogic; -- machine timer interrupt
|
mtime_irq_i : in std_ulogic; -- machine timer interrupt
|
-- fast interrupts (custom) --
|
-- fast interrupts (custom) --
|
firq_i : in std_ulogic_vector(7 downto 0);
|
firq_i : in std_ulogic_vector(15 downto 0);
|
firq_ack_o : out std_ulogic_vector(7 downto 0);
|
firq_ack_o : out std_ulogic_vector(15 downto 0);
|
-- system time input from MTIME --
|
-- system time input from MTIME --
|
time_i : in std_ulogic_vector(63 downto 0); -- current system time
|
time_i : in std_ulogic_vector(63 downto 0); -- current system time
|
-- physical memory protection --
|
-- physical memory protection --
|
pmp_addr_o : out pmp_addr_if_t; -- addresses
|
pmp_addr_o : out pmp_addr_if_t; -- addresses
|
pmp_ctrl_o : out pmp_ctrl_if_t; -- configs
|
pmp_ctrl_o : out pmp_ctrl_if_t; -- configs
|
| Line 212... |
Line 212... |
-- trap controller --
|
-- trap controller --
|
type trap_ctrl_t is record
|
type trap_ctrl_t is record
|
exc_buf : std_ulogic_vector(exception_width_c-1 downto 0);
|
exc_buf : std_ulogic_vector(exception_width_c-1 downto 0);
|
exc_fire : std_ulogic; -- set if there is a valid source in the exception buffer
|
exc_fire : std_ulogic; -- set if there is a valid source in the exception buffer
|
irq_buf : std_ulogic_vector(interrupt_width_c-1 downto 0);
|
irq_buf : std_ulogic_vector(interrupt_width_c-1 downto 0);
|
firq_sync : std_ulogic_vector(7 downto 0);
|
firq_sync : std_ulogic_vector(15 downto 0);
|
irq_fire : std_ulogic; -- set if there is a valid source in the interrupt buffer
|
irq_fire : std_ulogic; -- set if there is a valid source in the interrupt buffer
|
exc_ack : std_ulogic; -- acknowledge all exceptions
|
exc_ack : std_ulogic; -- acknowledge all exceptions
|
irq_ack : std_ulogic_vector(interrupt_width_c-1 downto 0); -- acknowledge specific interrupt
|
irq_ack : std_ulogic_vector(interrupt_width_c-1 downto 0); -- acknowledge specific interrupt
|
irq_ack_nxt : std_ulogic_vector(interrupt_width_c-1 downto 0);
|
irq_ack_nxt : std_ulogic_vector(interrupt_width_c-1 downto 0);
|
cause : std_ulogic_vector(5 downto 0); -- trap ID for mcause CSR
|
cause : std_ulogic_vector(5 downto 0); -- trap ID for mcause CSR
|
| Line 275... |
Line 275... |
mstatus_mpp : std_ulogic_vector(1 downto 0); -- mstatus.MPP: machine previous privilege mode
|
mstatus_mpp : std_ulogic_vector(1 downto 0); -- mstatus.MPP: machine previous privilege mode
|
--
|
--
|
mie_msie : std_ulogic; -- mie.MSIE: machine software interrupt enable (R/W)
|
mie_msie : std_ulogic; -- mie.MSIE: machine software interrupt enable (R/W)
|
mie_meie : std_ulogic; -- mie.MEIE: machine external interrupt enable (R/W)
|
mie_meie : std_ulogic; -- mie.MEIE: machine external interrupt enable (R/W)
|
mie_mtie : std_ulogic; -- mie.MEIE: machine timer interrupt enable (R/W)
|
mie_mtie : std_ulogic; -- mie.MEIE: machine timer interrupt enable (R/W)
|
mie_firqe : std_ulogic_vector(7 downto 0); -- mie.firq*e: fast interrupt enabled (R/W)
|
mie_firqe : std_ulogic_vector(15 downto 0); -- mie.firq*e: fast interrupt enabled (R/W)
|
--
|
--
|
mcounteren_cy : std_ulogic; -- mcounteren.cy: allow cycle[h] access from user-mode
|
mcounteren_cy : std_ulogic; -- mcounteren.cy: allow cycle[h] access from user-mode
|
mcounteren_tm : std_ulogic; -- mcounteren.tm: allow time[h] access from user-mode
|
mcounteren_tm : std_ulogic; -- mcounteren.tm: allow time[h] access from user-mode
|
mcounteren_ir : std_ulogic; -- mcounteren.ir: allow instret[h] access from user-mode
|
mcounteren_ir : std_ulogic; -- mcounteren.ir: allow instret[h] access from user-mode
|
mcounteren_hpm : std_ulogic_vector(HPM_NUM_CNTS-1 downto 0); -- mcounteren.hpmx: allow mhpmcounterx[h] access from user-mode
|
mcounteren_hpm : std_ulogic_vector(HPM_NUM_CNTS-1 downto 0); -- mcounteren.hpmx: allow mhpmcounterx[h] access from user-mode
|
| Line 1187... |
Line 1187... |
execute_engine.state_nxt <= DISPATCH;
|
execute_engine.state_nxt <= DISPATCH;
|
elsif (bus_d_wait_i = '0') then -- wait for bus to finish transaction
|
elsif (bus_d_wait_i = '0') then -- wait for bus to finish transaction
|
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') or (decode_aux.is_atomic_lr = '1') or (decode_aux.is_atomic_sc = '1') then -- load / load-reservate / store conditional
|
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') or (decode_aux.is_atomic_lr = '1') or (decode_aux.is_atomic_sc = '1') then -- load / load-reservate / store conditional
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
|
end if;
|
end if;
|
atomic_ctrl.env_end <= '1'; -- normal end of LOCKED (atomic) memory access environment
|
atomic_ctrl.env_end <= not decode_aux.is_atomic_lr; -- normal end of LOCKED (atomic) memory access environment - if we are not starting it via LR instruction
|
execute_engine.state_nxt <= DISPATCH;
|
execute_engine.state_nxt <= DISPATCH;
|
end if;
|
end if;
|
|
|
|
|
when others => -- undefined
|
when others => -- undefined
|
| Line 1601... |
Line 1601... |
trap_ctrl.exc_buf(exception_iillegal_c) <= (trap_ctrl.exc_buf(exception_iillegal_c) or trap_ctrl.instr_il) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_iillegal_c) <= (trap_ctrl.exc_buf(exception_iillegal_c) or trap_ctrl.instr_il) and (not trap_ctrl.exc_ack);
|
-- interrupt buffer: machine software/external/timer interrupt
|
-- interrupt buffer: machine software/external/timer interrupt
|
trap_ctrl.irq_buf(interrupt_msw_irq_c) <= csr.mie_msie and (trap_ctrl.irq_buf(interrupt_msw_irq_c) or msw_irq_i) and (not (trap_ctrl.irq_ack(interrupt_msw_irq_c) or csr.mip_clear(interrupt_msw_irq_c)));
|
trap_ctrl.irq_buf(interrupt_msw_irq_c) <= csr.mie_msie and (trap_ctrl.irq_buf(interrupt_msw_irq_c) or msw_irq_i) and (not (trap_ctrl.irq_ack(interrupt_msw_irq_c) or csr.mip_clear(interrupt_msw_irq_c)));
|
trap_ctrl.irq_buf(interrupt_mext_irq_c) <= csr.mie_meie and (trap_ctrl.irq_buf(interrupt_mext_irq_c) or mext_irq_i) and (not (trap_ctrl.irq_ack(interrupt_mext_irq_c) or csr.mip_clear(interrupt_mext_irq_c)));
|
trap_ctrl.irq_buf(interrupt_mext_irq_c) <= csr.mie_meie and (trap_ctrl.irq_buf(interrupt_mext_irq_c) or mext_irq_i) and (not (trap_ctrl.irq_ack(interrupt_mext_irq_c) or csr.mip_clear(interrupt_mext_irq_c)));
|
trap_ctrl.irq_buf(interrupt_mtime_irq_c) <= csr.mie_mtie and (trap_ctrl.irq_buf(interrupt_mtime_irq_c) or mtime_irq_i) and (not (trap_ctrl.irq_ack(interrupt_mtime_irq_c) or csr.mip_clear(interrupt_mtime_irq_c)));
|
trap_ctrl.irq_buf(interrupt_mtime_irq_c) <= csr.mie_mtie and (trap_ctrl.irq_buf(interrupt_mtime_irq_c) or mtime_irq_i) and (not (trap_ctrl.irq_ack(interrupt_mtime_irq_c) or csr.mip_clear(interrupt_mtime_irq_c)));
|
-- interrupt buffer: custom fast interrupts
|
-- interrupt buffer: NEORV32-specific fast interrupts
|
trap_ctrl.firq_sync <= firq_i;
|
trap_ctrl.firq_sync <= firq_i;
|
--
|
for i in 0 to 15 loop
|
trap_ctrl.irq_buf(interrupt_firq_0_c) <= csr.mie_firqe(0) and (trap_ctrl.irq_buf(interrupt_firq_0_c) or trap_ctrl.firq_sync(0)) and (not (trap_ctrl.irq_ack(interrupt_firq_0_c) or csr.mip_clear(interrupt_firq_0_c)));
|
trap_ctrl.irq_buf(interrupt_firq_0_c+i) <= csr.mie_firqe(i) and (trap_ctrl.irq_buf(interrupt_firq_0_c+i) or trap_ctrl.firq_sync(i)) and (not (trap_ctrl.irq_ack(interrupt_firq_0_c+i) or csr.mip_clear(interrupt_firq_0_c+i)));
|
trap_ctrl.irq_buf(interrupt_firq_1_c) <= csr.mie_firqe(1) and (trap_ctrl.irq_buf(interrupt_firq_1_c) or trap_ctrl.firq_sync(1)) and (not (trap_ctrl.irq_ack(interrupt_firq_1_c) or csr.mip_clear(interrupt_firq_1_c)));
|
end loop;
|
trap_ctrl.irq_buf(interrupt_firq_2_c) <= csr.mie_firqe(2) and (trap_ctrl.irq_buf(interrupt_firq_2_c) or trap_ctrl.firq_sync(2)) and (not (trap_ctrl.irq_ack(interrupt_firq_2_c) or csr.mip_clear(interrupt_firq_2_c)));
|
|
trap_ctrl.irq_buf(interrupt_firq_3_c) <= csr.mie_firqe(3) and (trap_ctrl.irq_buf(interrupt_firq_3_c) or trap_ctrl.firq_sync(3)) and (not (trap_ctrl.irq_ack(interrupt_firq_3_c) or csr.mip_clear(interrupt_firq_3_c)));
|
|
trap_ctrl.irq_buf(interrupt_firq_4_c) <= csr.mie_firqe(4) and (trap_ctrl.irq_buf(interrupt_firq_4_c) or trap_ctrl.firq_sync(4)) and (not (trap_ctrl.irq_ack(interrupt_firq_4_c) or csr.mip_clear(interrupt_firq_4_c)));
|
|
trap_ctrl.irq_buf(interrupt_firq_5_c) <= csr.mie_firqe(5) and (trap_ctrl.irq_buf(interrupt_firq_5_c) or trap_ctrl.firq_sync(5)) and (not (trap_ctrl.irq_ack(interrupt_firq_5_c) or csr.mip_clear(interrupt_firq_5_c)));
|
|
trap_ctrl.irq_buf(interrupt_firq_6_c) <= csr.mie_firqe(6) and (trap_ctrl.irq_buf(interrupt_firq_6_c) or trap_ctrl.firq_sync(6)) and (not (trap_ctrl.irq_ack(interrupt_firq_6_c) or csr.mip_clear(interrupt_firq_6_c)));
|
|
trap_ctrl.irq_buf(interrupt_firq_7_c) <= csr.mie_firqe(7) and (trap_ctrl.irq_buf(interrupt_firq_7_c) or trap_ctrl.firq_sync(7)) and (not (trap_ctrl.irq_ack(interrupt_firq_7_c) or csr.mip_clear(interrupt_firq_7_c)));
|
|
-- trap control --
|
-- trap control --
|
if (trap_ctrl.env_start = '0') then -- no started trap handler
|
if (trap_ctrl.env_start = '0') then -- no started trap handler
|
if (trap_ctrl.exc_fire = '1') or ((trap_ctrl.irq_fire = '1') and -- exception/IRQ detected!
|
if (trap_ctrl.exc_fire = '1') or ((trap_ctrl.irq_fire = '1') and -- exception/IRQ detected!
|
((execute_engine.state = EXECUTE) or (execute_engine.state = TRAP))) then -- sample IRQs in EXECUTE or TRAP state only to continue execution even if permanent IRQ
|
((execute_engine.state = EXECUTE) or (execute_engine.state = TRAP))) then -- sample IRQs in EXECUTE or TRAP state only to continue execution even if permanent IRQ
|
trap_ctrl.cause <= trap_ctrl.cause_nxt; -- capture source ID for program (for mcause csr)
|
trap_ctrl.cause <= trap_ctrl.cause_nxt; -- capture source ID for program (for mcause csr)
|
| Line 1640... |
Line 1634... |
|
|
-- current pending interrupts (for CSR.MIP register) --
|
-- current pending interrupts (for CSR.MIP register) --
|
csr.mip_status <= trap_ctrl.irq_buf;
|
csr.mip_status <= trap_ctrl.irq_buf;
|
|
|
-- acknowledge mask output --
|
-- acknowledge mask output --
|
firq_ack_o <= trap_ctrl.irq_ack(interrupt_firq_7_c downto interrupt_firq_0_c);
|
firq_ack_o <= trap_ctrl.irq_ack(interrupt_firq_15_c downto interrupt_firq_0_c);
|
|
|
|
|
-- Trap Priority Encoder ------------------------------------------------------------------
|
-- Trap Priority Encoder ------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
trap_priority: process(trap_ctrl)
|
trap_priority: process(trap_ctrl)
|
| Line 1710... |
Line 1704... |
-- interrupt: 1.23 fast interrupt channel 7 --
|
-- interrupt: 1.23 fast interrupt channel 7 --
|
elsif (trap_ctrl.irq_buf(interrupt_firq_7_c) = '1') then
|
elsif (trap_ctrl.irq_buf(interrupt_firq_7_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_firq7_c;
|
trap_ctrl.cause_nxt <= trap_firq7_c;
|
trap_ctrl.irq_ack_nxt(interrupt_firq_7_c) <= '1';
|
trap_ctrl.irq_ack_nxt(interrupt_firq_7_c) <= '1';
|
|
|
|
-- interrupt: 1.24 fast interrupt channel 8 --
|
|
elsif (trap_ctrl.irq_buf(interrupt_firq_8_c) = '1') then
|
|
trap_ctrl.cause_nxt <= trap_firq8_c;
|
|
trap_ctrl.irq_ack_nxt(interrupt_firq_8_c) <= '1';
|
|
|
|
-- interrupt: 1.25 fast interrupt channel 9 --
|
|
elsif (trap_ctrl.irq_buf(interrupt_firq_9_c) = '1') then
|
|
trap_ctrl.cause_nxt <= trap_firq9_c;
|
|
trap_ctrl.irq_ack_nxt(interrupt_firq_9_c) <= '1';
|
|
|
|
-- interrupt: 1.26 fast interrupt channel 10 --
|
|
elsif (trap_ctrl.irq_buf(interrupt_firq_10_c) = '1') then
|
|
trap_ctrl.cause_nxt <= trap_firq10_c;
|
|
trap_ctrl.irq_ack_nxt(interrupt_firq_10_c) <= '1';
|
|
|
|
-- interrupt: 1.27 fast interrupt channel 11 --
|
|
elsif (trap_ctrl.irq_buf(interrupt_firq_11_c) = '1') then
|
|
trap_ctrl.cause_nxt <= trap_firq11_c;
|
|
trap_ctrl.irq_ack_nxt(interrupt_firq_11_c) <= '1';
|
|
|
|
-- interrupt: 1.28 fast interrupt channel 12 --
|
|
elsif (trap_ctrl.irq_buf(interrupt_firq_12_c) = '1') then
|
|
trap_ctrl.cause_nxt <= trap_firq12_c;
|
|
trap_ctrl.irq_ack_nxt(interrupt_firq_12_c) <= '1';
|
|
|
|
-- interrupt: 1.29 fast interrupt channel 13 --
|
|
elsif (trap_ctrl.irq_buf(interrupt_firq_13_c) = '1') then
|
|
trap_ctrl.cause_nxt <= trap_firq13_c;
|
|
trap_ctrl.irq_ack_nxt(interrupt_firq_13_c) <= '1';
|
|
|
|
-- interrupt: 1.30 fast interrupt channel 14 --
|
|
elsif (trap_ctrl.irq_buf(interrupt_firq_14_c) = '1') then
|
|
trap_ctrl.cause_nxt <= trap_firq14_c;
|
|
trap_ctrl.irq_ack_nxt(interrupt_firq_14_c) <= '1';
|
|
|
|
-- interrupt: 1.31 fast interrupt channel 15 --
|
|
elsif (trap_ctrl.irq_buf(interrupt_firq_15_c) = '1') then
|
|
trap_ctrl.cause_nxt <= trap_firq15_c;
|
|
trap_ctrl.irq_ack_nxt(interrupt_firq_15_c) <= '1';
|
|
|
|
|
-- the following traps are caused by *synchronous* exceptions (= 'classic' exceptions)
|
-- the following traps are caused by *synchronous* exceptions (= 'classic' exceptions)
|
-- here we do not need a specific acknowledge mask since only one exception (the one
|
-- here we do not need a specific acknowledge mask since only one exception (the one
|
-- with highest priority) is evaluated at once
|
-- with highest priority) is evaluated at once
|
|
|
| Line 1884... |
Line 1918... |
end if;
|
end if;
|
when csr_mie_c => -- R/W: mie - machine interrupt enable register
|
when csr_mie_c => -- R/W: mie - machine interrupt enable register
|
csr.mie_msie <= csr.wdata(03); -- machine SW IRQ enable
|
csr.mie_msie <= csr.wdata(03); -- machine SW IRQ enable
|
csr.mie_mtie <= csr.wdata(07); -- machine TIMER IRQ enable
|
csr.mie_mtie <= csr.wdata(07); -- machine TIMER IRQ enable
|
csr.mie_meie <= csr.wdata(11); -- machine EXT IRQ enable
|
csr.mie_meie <= csr.wdata(11); -- machine EXT IRQ enable
|
--
|
for i in 0 to 15 loop -- fast interrupt channels 0..15
|
csr.mie_firqe(0) <= csr.wdata(16); -- fast interrupt channel 0
|
csr.mie_firqe(i) <= csr.wdata(16+i);
|
csr.mie_firqe(1) <= csr.wdata(17); -- fast interrupt channel 1
|
end loop; -- i
|
csr.mie_firqe(2) <= csr.wdata(18); -- fast interrupt channel 2
|
|
csr.mie_firqe(3) <= csr.wdata(19); -- fast interrupt channel 3
|
|
csr.mie_firqe(4) <= csr.wdata(20); -- fast interrupt channel 4
|
|
csr.mie_firqe(5) <= csr.wdata(21); -- fast interrupt channel 5
|
|
csr.mie_firqe(6) <= csr.wdata(22); -- fast interrupt channel 6
|
|
csr.mie_firqe(7) <= csr.wdata(22); -- fast interrupt channel 7
|
|
when csr_mtvec_c => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions)
|
when csr_mtvec_c => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions)
|
csr.mtvec <= csr.wdata(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0
|
csr.mtvec <= csr.wdata(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0
|
when csr_mcounteren_c => -- R/W: machine counter enable register
|
when csr_mcounteren_c => -- R/W: machine counter enable register
|
csr.mcounteren_cy <= csr.wdata(0); -- enable user-level access to cycle[h]
|
csr.mcounteren_cy <= csr.wdata(0); -- enable user-level access to cycle[h]
|
csr.mcounteren_tm <= csr.wdata(1); -- enable user-level access to time[h]
|
csr.mcounteren_tm <= csr.wdata(1); -- enable user-level access to time[h]
|
| Line 1917... |
Line 1945... |
csr.mtval <= csr.wdata;
|
csr.mtval <= csr.wdata;
|
when csr_mip_c => -- R/W: mip - machine interrupt pending
|
when csr_mip_c => -- R/W: mip - machine interrupt pending
|
csr.mip_clear(interrupt_msw_irq_c) <= not csr.wdata(03);
|
csr.mip_clear(interrupt_msw_irq_c) <= not csr.wdata(03);
|
csr.mip_clear(interrupt_mtime_irq_c) <= not csr.wdata(07);
|
csr.mip_clear(interrupt_mtime_irq_c) <= not csr.wdata(07);
|
csr.mip_clear(interrupt_mext_irq_c) <= not csr.wdata(11);
|
csr.mip_clear(interrupt_mext_irq_c) <= not csr.wdata(11);
|
--
|
for i in 0 to 15 loop -- fast interrupt channels 0..15
|
csr.mip_clear(interrupt_firq_0_c) <= not csr.wdata(16);
|
csr.mip_clear(interrupt_firq_0_c+i) <= not csr.wdata(16+i);
|
csr.mip_clear(interrupt_firq_1_c) <= not csr.wdata(17);
|
end loop; -- i
|
csr.mip_clear(interrupt_firq_2_c) <= not csr.wdata(18);
|
|
csr.mip_clear(interrupt_firq_3_c) <= not csr.wdata(19);
|
|
csr.mip_clear(interrupt_firq_4_c) <= not csr.wdata(20);
|
|
csr.mip_clear(interrupt_firq_5_c) <= not csr.wdata(21);
|
|
csr.mip_clear(interrupt_firq_6_c) <= not csr.wdata(22);
|
|
csr.mip_clear(interrupt_firq_7_c) <= not csr.wdata(23);
|
|
|
|
-- physical memory protection: R/W: pmpcfg* - PMP configuration registers --
|
-- physical memory protection: R/W: pmpcfg* - PMP configuration registers --
|
-- --------------------------------------------------------------------
|
-- --------------------------------------------------------------------
|
when csr_pmpcfg0_c | csr_pmpcfg1_c | csr_pmpcfg2_c | csr_pmpcfg3_c | csr_pmpcfg4_c | csr_pmpcfg5_c | csr_pmpcfg6_c | csr_pmpcfg7_c |
|
when csr_pmpcfg0_c | csr_pmpcfg1_c | csr_pmpcfg2_c | csr_pmpcfg3_c | csr_pmpcfg4_c | csr_pmpcfg5_c | csr_pmpcfg6_c | csr_pmpcfg7_c |
|
csr_pmpcfg8_c | csr_pmpcfg9_c | csr_pmpcfg10_c | csr_pmpcfg11_c | csr_pmpcfg12_c | csr_pmpcfg13_c | csr_pmpcfg14_c | csr_pmpcfg15_c =>
|
csr_pmpcfg8_c | csr_pmpcfg9_c | csr_pmpcfg10_c | csr_pmpcfg11_c | csr_pmpcfg12_c | csr_pmpcfg13_c | csr_pmpcfg14_c | csr_pmpcfg15_c =>
|
| Line 2233... |
Line 2255... |
csr.rdata(31) <= '0'; -- 32-bit architecture (MXL hi)
|
csr.rdata(31) <= '0'; -- 32-bit architecture (MXL hi)
|
when csr_mie_c => -- R/W: mie - machine interrupt-enable register
|
when csr_mie_c => -- R/W: mie - machine interrupt-enable register
|
csr.rdata(03) <= csr.mie_msie; -- machine software IRQ enable
|
csr.rdata(03) <= csr.mie_msie; -- machine software IRQ enable
|
csr.rdata(07) <= csr.mie_mtie; -- machine timer IRQ enable
|
csr.rdata(07) <= csr.mie_mtie; -- machine timer IRQ enable
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csr.rdata(11) <= csr.mie_meie; -- machine external IRQ enable
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csr.rdata(11) <= csr.mie_meie; -- machine external IRQ enable
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--
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for i in 0 to 15 loop -- fast interrupt channels 0..15 enable
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csr.rdata(16) <= csr.mie_firqe(0); -- fast interrupt channel 0
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csr.rdata(16+i) <= csr.mie_firqe(i);
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csr.rdata(17) <= csr.mie_firqe(1); -- fast interrupt channel 1
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end loop; -- i
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csr.rdata(18) <= csr.mie_firqe(2); -- fast interrupt channel 2
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csr.rdata(19) <= csr.mie_firqe(3); -- fast interrupt channel 3
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csr.rdata(20) <= csr.mie_firqe(4); -- fast interrupt channel 4
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csr.rdata(21) <= csr.mie_firqe(5); -- fast interrupt channel 5
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csr.rdata(22) <= csr.mie_firqe(6); -- fast interrupt channel 6
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csr.rdata(23) <= csr.mie_firqe(7); -- fast interrupt channel 7
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when csr_mtvec_c => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions)
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when csr_mtvec_c => -- R/W: mtvec - machine trap-handler base address (for ALL exceptions)
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csr.rdata <= csr.mtvec(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0
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csr.rdata <= csr.mtvec(data_width_c-1 downto 2) & "00"; -- mtvec.MODE=0
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when csr_mcounteren_c => -- R/W: machine counter enable register
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when csr_mcounteren_c => -- R/W: machine counter enable register
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csr.rdata(0) <= csr.mcounteren_cy; -- enable user-level access to cycle[h]
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csr.rdata(0) <= csr.mcounteren_cy; -- enable user-level access to cycle[h]
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csr.rdata(1) <= csr.mcounteren_tm; -- enable user-level access to time[h]
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csr.rdata(1) <= csr.mcounteren_tm; -- enable user-level access to time[h]
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| Line 2263... |
Line 2279... |
csr.rdata <= csr.mtval;
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csr.rdata <= csr.mtval;
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when csr_mip_c => -- R/W: mip - machine interrupt pending
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when csr_mip_c => -- R/W: mip - machine interrupt pending
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csr.rdata(03) <= csr.mip_status(interrupt_msw_irq_c);
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csr.rdata(03) <= csr.mip_status(interrupt_msw_irq_c);
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csr.rdata(07) <= csr.mip_status(interrupt_mtime_irq_c);
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csr.rdata(07) <= csr.mip_status(interrupt_mtime_irq_c);
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csr.rdata(11) <= csr.mip_status(interrupt_mext_irq_c);
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csr.rdata(11) <= csr.mip_status(interrupt_mext_irq_c);
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--
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for i in 0 to 15 loop -- fast interrupt channels 0..15 pending
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csr.rdata(16) <= csr.mip_status(interrupt_firq_0_c);
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csr.rdata(16+i) <= csr.mip_status(interrupt_firq_0_c+i);
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csr.rdata(17) <= csr.mip_status(interrupt_firq_1_c);
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end loop; -- i
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csr.rdata(18) <= csr.mip_status(interrupt_firq_2_c);
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csr.rdata(19) <= csr.mip_status(interrupt_firq_3_c);
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csr.rdata(20) <= csr.mip_status(interrupt_firq_4_c);
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csr.rdata(21) <= csr.mip_status(interrupt_firq_5_c);
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csr.rdata(22) <= csr.mip_status(interrupt_firq_6_c);
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csr.rdata(23) <= csr.mip_status(interrupt_firq_7_c);
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-- physical memory protection - configuration --
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-- physical memory protection - configuration --
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when csr_pmpcfg0_c => csr.rdata <= csr.pmpcfg_rd(03) & csr.pmpcfg_rd(02) & csr.pmpcfg_rd(01) & csr.pmpcfg_rd(00); -- R/W: pmpcfg0
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when csr_pmpcfg0_c => csr.rdata <= csr.pmpcfg_rd(03) & csr.pmpcfg_rd(02) & csr.pmpcfg_rd(01) & csr.pmpcfg_rd(00); -- R/W: pmpcfg0
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when csr_pmpcfg1_c => csr.rdata <= csr.pmpcfg_rd(07) & csr.pmpcfg_rd(06) & csr.pmpcfg_rd(05) & csr.pmpcfg_rd(04); -- R/W: pmpcfg1
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when csr_pmpcfg1_c => csr.rdata <= csr.pmpcfg_rd(07) & csr.pmpcfg_rd(06) & csr.pmpcfg_rd(05) & csr.pmpcfg_rd(04); -- R/W: pmpcfg1
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when csr_pmpcfg2_c => csr.rdata <= csr.pmpcfg_rd(11) & csr.pmpcfg_rd(10) & csr.pmpcfg_rd(09) & csr.pmpcfg_rd(08); -- R/W: pmpcfg2
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when csr_pmpcfg2_c => csr.rdata <= csr.pmpcfg_rd(11) & csr.pmpcfg_rd(10) & csr.pmpcfg_rd(09) & csr.pmpcfg_rd(08); -- R/W: pmpcfg2
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