| Line 46... |
Line 46... |
use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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|
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entity neorv32_cpu_control is
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entity neorv32_cpu_control is
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generic (
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generic (
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-- General --
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-- General --
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HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit)
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HW_THREAD_ID : natural; -- hardware thread id (32-bit)
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CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0) := x"00000000"; -- cpu boot address
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CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0); -- cpu boot address
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CPU_DEBUG_ADDR : std_ulogic_vector(31 downto 0) := x"00000000"; -- cpu debug mode start address
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CPU_DEBUG_ADDR : std_ulogic_vector(31 downto 0); -- cpu debug mode start address
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
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CPU_EXTENSION_RISCV_A : boolean; -- implement atomic extension?
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_C : boolean; -- implement compressed extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E : boolean; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M : boolean; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
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CPU_EXTENSION_RISCV_U : boolean; -- implement user mode extension?
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CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT reg!)
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CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!)
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr : boolean; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension?
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CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
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CPU_EXTENSION_RISCV_DEBUG : boolean := false; -- implement CPU debug mode?
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CPU_EXTENSION_RISCV_DEBUG : boolean; -- implement CPU debug mode?
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-- Extension Options --
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-- Extension Options --
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CPU_CNT_WIDTH : natural := 64; -- total width of CPU cycle and instret counters (0..64)
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CPU_CNT_WIDTH : natural; -- total width of CPU cycle and instret counters (0..64)
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CPU_IPB_ENTRIES : natural; -- entries is instruction prefetch buffer, has to be a power of 2
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-- Physical memory protection (PMP) --
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-- Physical memory protection (PMP) --
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PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
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PMP_NUM_REGIONS : natural; -- number of regions (0..64)
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PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
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PMP_MIN_GRANULARITY : natural; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
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-- Hardware Performance Monitors (HPM) --
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-- Hardware Performance Monitors (HPM) --
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HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29)
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HPM_NUM_CNTS : natural; -- number of implemented HPM counters (0..29)
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HPM_CNT_WIDTH : natural := 40 -- total size of HPM counters (0..64)
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HPM_CNT_WIDTH : natural -- total size of HPM counters (0..64)
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);
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);
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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rstn_i : in std_ulogic; -- global reset, low-active, async
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| Line 272... |
Line 273... |
re : std_ulogic; -- csr read enable
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re : std_ulogic; -- csr read enable
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re_nxt : std_ulogic;
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re_nxt : std_ulogic;
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wdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr write data
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wdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr write data
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rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
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rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
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--
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--
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mstatus_fs : std_ulogic; -- mstatus.FS: FPU status (single-bit, only OFF and DIRTY states)
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mstatus_mie : std_ulogic; -- mstatus.MIE: global IRQ enable (R/W)
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mstatus_mie : std_ulogic; -- mstatus.MIE: global IRQ enable (R/W)
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mstatus_mpie : std_ulogic; -- mstatus.MPIE: previous global IRQ enable (R/W)
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mstatus_mpie : std_ulogic; -- mstatus.MPIE: previous global IRQ enable (R/W)
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mstatus_mpp : std_ulogic_vector(1 downto 0); -- mstatus.MPP: machine previous privilege mode
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mstatus_mpp : std_ulogic_vector(1 downto 0); -- mstatus.MPP: machine previous privilege mode
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mstatus_tw : std_ulogic; -- mstatus:TW trigger illegal instruction exception if WFI is executed outside of M-mode
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--
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--
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mie_msie : std_ulogic; -- mie.MSIE: machine software interrupt enable (R/W)
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mie_msie : std_ulogic; -- mie.MSIE: machine software interrupt enable (R/W)
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mie_meie : std_ulogic; -- mie.MEIE: machine external interrupt enable (R/W)
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mie_meie : std_ulogic; -- mie.MEIE: machine external interrupt enable (R/W)
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mie_mtie : std_ulogic; -- mie.MEIE: machine timer interrupt enable (R/W)
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mie_mtie : std_ulogic; -- mie.MEIE: machine timer interrupt enable (R/W)
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mie_firqe : std_ulogic_vector(15 downto 0); -- mie.firq*e: fast interrupt enabled (R/W)
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mie_firqe : std_ulogic_vector(15 downto 0); -- mie.firq*e: fast interrupt enabled (R/W)
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| Line 456... |
Line 459... |
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-- Instruction Prefetch Buffer (FIFO) -----------------------------------------------------
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-- Instruction Prefetch Buffer (FIFO) -----------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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instr_prefetch_buffer: neorv32_fifo
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instr_prefetch_buffer: neorv32_fifo
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generic map (
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generic map (
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FIFO_DEPTH => ipb_entries_c, -- number of fifo entries; has to be a power of two; min 1
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FIFO_DEPTH => CPU_IPB_ENTRIES, -- number of fifo entries; has to be a power of two; min 1
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FIFO_WIDTH => ipb.wdata'length, -- size of data elements in fifo
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FIFO_WIDTH => ipb.wdata'length, -- size of data elements in fifo
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FIFO_RSYNC => false, -- we NEED to read data asynchronously
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FIFO_RSYNC => false, -- we NEED to read data asynchronously
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FIFO_SAFE => false -- no safe access required (ensured by FIFO-external control)
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FIFO_SAFE => false -- no safe access required (ensured by FIFO-external control)
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)
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)
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port map (
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port map (
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Line 615... |
-- Instruction Execution
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-- Instruction Execution
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-- ****************************************************************************************************************************
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-- ****************************************************************************************************************************
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-- Immediate Generator --------------------------------------------------------------------
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-- Immediate Generator --------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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imm_gen: process(execute_engine.i_reg, rstn_i, clk_i)
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imm_gen: process(rstn_i, clk_i)
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variable opcode_v : std_ulogic_vector(6 downto 0);
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variable opcode_v : std_ulogic_vector(6 downto 0);
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begin
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begin
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opcode_v := execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c+2) & "11";
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if (rstn_i = '0') then
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if (rstn_i = '0') then
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imm_o <= (others => def_rst_val_c);
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imm_o <= (others => def_rst_val_c);
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elsif rising_edge(clk_i) then
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elsif rising_edge(clk_i) then
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if (execute_engine.state = BRANCH) then -- next_PC as immediate for jump-and-link operations (=return address) via ALU.MOV_B
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if (execute_engine.state = BRANCH) then -- next_PC as immediate for jump-and-link operations (=return address) via ALU.MOV_B
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imm_o <= execute_engine.next_pc;
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imm_o <= execute_engine.next_pc;
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else -- "normal" immediate from instruction word
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else -- "normal" immediate from instruction word
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opcode_v := execute_engine.i_reg(instr_opcode_msb_c downto instr_opcode_lsb_c+2) & "11";
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case opcode_v is -- save some bits here, the two LSBs are always "11" for rv32
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case opcode_v is -- save some bits here, the two LSBs are always "11" for rv32
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when opcode_store_c => -- S-immediate
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when opcode_store_c => -- S-immediate
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imm_o(31 downto 11) <= (others => execute_engine.i_reg(31)); -- sign extension
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imm_o(31 downto 11) <= (others => execute_engine.i_reg(31)); -- sign extension
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imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
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imm_o(10 downto 05) <= execute_engine.i_reg(30 downto 25);
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imm_o(04 downto 01) <= execute_engine.i_reg(11 downto 08);
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imm_o(04 downto 01) <= execute_engine.i_reg(11 downto 08);
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| Line 688... |
Line 691... |
execute_engine.pc <= CPU_BOOT_ADDR(data_width_c-1 downto 1) & '0';
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execute_engine.pc <= CPU_BOOT_ADDR(data_width_c-1 downto 1) & '0';
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execute_engine.state <= SYS_WAIT;
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execute_engine.state <= SYS_WAIT;
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execute_engine.sleep <= '0';
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execute_engine.sleep <= '0';
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execute_engine.branched <= '1'; -- reset is a branch from "somewhere"
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execute_engine.branched <= '1'; -- reset is a branch from "somewhere"
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-- no dedicated RESET required --
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-- no dedicated RESET required --
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execute_engine.state_prev <= SYS_WAIT;
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execute_engine.state_prev <= SYS_WAIT; -- actual reset value is not relevant
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execute_engine.i_reg <= (others => def_rst_val_c);
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execute_engine.i_reg <= (others => def_rst_val_c);
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execute_engine.is_ci <= def_rst_val_c;
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execute_engine.is_ci <= def_rst_val_c;
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execute_engine.last_pc <= (others => def_rst_val_c);
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execute_engine.last_pc <= (others => def_rst_val_c);
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execute_engine.i_reg_last <= (others => def_rst_val_c);
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execute_engine.i_reg_last <= (others => def_rst_val_c);
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execute_engine.next_pc <= (others => def_rst_val_c);
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execute_engine.next_pc <= (others => def_rst_val_c);
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| Line 915... |
Line 918... |
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-- state machine --
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-- state machine --
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case execute_engine.state is
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case execute_engine.state is
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when SYS_WAIT => -- System delay cycle (used to wait for side effects to kick in) [and to init r0 with zero if it is a physical register]
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when SYS_WAIT => -- System delay cycle (to let side effects kick in)
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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-- set reg_file's r0 to zero --
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if (rf_r0_is_reg_c = true) then -- is r0 implemented as physical register, which has to be set to zero?
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ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_csrr_c; -- hacky! CSR read-access without a valid CSR-read -> results zero
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ctrl_nxt(ctrl_rf_r0_we_c) <= '1'; -- force RF write access and force rd=r0
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end if;
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--
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execute_engine.state_nxt <= DISPATCH;
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execute_engine.state_nxt <= DISPATCH;
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when DISPATCH => -- Get new command from instruction issue engine
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when DISPATCH => -- Get new command from instruction issue engine
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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| Line 1101... |
Line 1098... |
execute_engine.state_nxt <= SYS_WAIT;
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execute_engine.state_nxt <= SYS_WAIT;
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end if;
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end if;
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when opcode_fop_c => -- floating-point operations
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when opcode_fop_c => -- floating-point operations
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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if (CPU_EXTENSION_RISCV_Zfinx = true) and (decode_aux.is_float_op = '1') then
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if (CPU_EXTENSION_RISCV_Zfinx = true) and (decode_aux.is_float_op = '1') and (csr.mstatus_fs = '1') then
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ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_fpu_c; -- trigger FPU CP
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ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_fpu_c; -- trigger FPU CP
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ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_copro_c;
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ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_cmd_copro_c;
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execute_engine.state_nxt <= ALU_WAIT;
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execute_engine.state_nxt <= ALU_WAIT;
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else
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else
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execute_engine.state_nxt <= SYS_WAIT;
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execute_engine.state_nxt <= SYS_WAIT;
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| Line 1118... |
Line 1115... |
end case;
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end case;
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when SYS_ENV => -- system environment operation - execution
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when SYS_ENV => -- system environment operation - execution
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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execute_engine.state_nxt <= SYS_WAIT;
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execute_engine.state_nxt <= SYS_WAIT; -- default
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case decode_aux.sys_env_cmd is -- use a simplified input here (with permanent zeros)
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case decode_aux.sys_env_cmd is -- use a simplified input here (with permanent zeros)
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when funct12_ecall_c => trap_ctrl.env_call <= '1'; -- ECALL
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when funct12_ecall_c => trap_ctrl.env_call <= '1'; -- ECALL
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when funct12_ebreak_c => trap_ctrl.break_point <= '1'; -- EBREAK
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when funct12_ebreak_c => trap_ctrl.break_point <= '1'; -- EBREAK
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when funct12_mret_c => execute_engine.state_nxt <= TRAP_EXIT; -- MRET
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when funct12_wfi_c => execute_engine.sleep_nxt <= '1'; -- WFI
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when funct12_wfi_c => execute_engine.sleep_nxt <= '1'; -- WFI
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when funct12_mret_c => -- MRET
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if (CPU_EXTENSION_RISCV_U = true) and (csr.priv_m_mode = '1') then -- only allowed in M-mode
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execute_engine.state_nxt <= TRAP_EXIT;
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else
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NULL;
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end if;
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when funct12_dret_c => -- DRET
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when funct12_dret_c => -- DRET
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if (CPU_EXTENSION_RISCV_DEBUG = true) then
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if (CPU_EXTENSION_RISCV_DEBUG = true) and (debug_ctrl.running = '1') then -- only allowed in debug-mode
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execute_engine.state_nxt <= TRAP_EXIT;
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execute_engine.state_nxt <= TRAP_EXIT;
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debug_ctrl.dret <= '1';
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debug_ctrl.dret <= '1';
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else
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else
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NULL;
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NULL;
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end if;
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end if;
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| Line 1189... |
Line 1191... |
when FENCE_OP => -- fence operations - execution
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when FENCE_OP => -- fence operations - execution
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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execute_engine.state_nxt <= SYS_WAIT;
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execute_engine.state_nxt <= SYS_WAIT;
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-- FENCE.I --
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-- FENCE.I --
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if (CPU_EXTENSION_RISCV_Zifencei = true) then
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if (CPU_EXTENSION_RISCV_Zifencei = true) then
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execute_engine.pc_mux_sel <= '0'; -- linear next PC = start *new* instruction fetch with next instruction (only relevant for fence.i)
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execute_engine.pc_mux_sel <= '0'; -- linear next PC = start *new* instruction fetch with next instruction
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if (execute_engine.i_reg(instr_funct3_lsb_c) = funct3_fencei_c(0)) then
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if (execute_engine.i_reg(instr_funct3_lsb_c) = funct3_fencei_c(0)) then
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execute_engine.pc_we <= '1'; -- update PC
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execute_engine.pc_we <= '1'; -- update PC
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execute_engine.branched_nxt <= '1'; -- this is an actual branch
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execute_engine.branched_nxt <= '1'; -- this is an actual branch
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fetch_engine.reset <= '1'; -- trigger new instruction fetch from modified PC
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fetch_engine.reset <= '1'; -- trigger new instruction fetch from modified PC
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ctrl_nxt(ctrl_bus_fencei_c) <= '1';
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ctrl_nxt(ctrl_bus_fencei_c) <= '1';
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| Line 1231... |
Line 1233... |
when LOADSTORE_2 => -- wait for bus transaction to finish
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when LOADSTORE_2 => -- wait for bus transaction to finish
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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ctrl_nxt(ctrl_bus_mi_we_c) <= '1'; -- keep writing input data to MDI (only relevant for load (and SC.W) operations)
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ctrl_nxt(ctrl_bus_mi_we_c) <= '1'; -- keep writing input data to MDI (only relevant for load (and SC.W) operations)
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ctrl_nxt(ctrl_rf_in_mux_c) <= '1'; -- RF input = memory input (only relevant for LOADs)
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ctrl_nxt(ctrl_rf_in_mux_c) <= '1'; -- RF input = memory input (only relevant for LOADs)
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-- wait for memory response / exception --
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-- wait for memory response / exception --
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if (trap_ctrl.env_start = '1') then -- abort if exception
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if (trap_ctrl.env_start = '1') and -- only abort if BUS EXCEPTION
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((trap_ctrl.cause = trap_lma_c) or (trap_ctrl.cause = trap_lbe_c) or (trap_ctrl.cause = trap_sma_c) or (trap_ctrl.cause = trap_sbe_c)) then
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execute_engine.state_nxt <= SYS_WAIT;
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execute_engine.state_nxt <= SYS_WAIT;
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elsif (bus_d_wait_i = '0') then -- wait for bus to finish transaction
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elsif (bus_d_wait_i = '0') then -- wait for bus to finish transaction
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-- data write-back --
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-- data write-back --
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if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') or -- normal load
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if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') or -- normal load
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(decode_aux.is_atomic_lr = '1') or -- atomic load-reservate
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(decode_aux.is_atomic_lr = '1') or -- atomic load-reservate
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| Line 1279... |
Line 1282... |
csr_acc_valid <= '0'; -- default = invalid access
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csr_acc_valid <= '0'; -- default = invalid access
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case csr.addr is
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case csr.addr is
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|
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-- floating-point CSRs --
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-- floating-point CSRs --
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when csr_fflags_c | csr_frm_c | csr_fcsr_c =>
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when csr_fflags_c | csr_frm_c | csr_fcsr_c =>
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if (CPU_EXTENSION_RISCV_Zfinx = true) then
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if (CPU_EXTENSION_RISCV_Zfinx = true) and (csr.mstatus_fs = '1') then -- FPU implemented and enabled?
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csr_acc_valid <= '1'; -- full access for everyone if Zfinx extension is implemented
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csr_acc_valid <= '1'; -- full access for everyone
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else
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else
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NULL;
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NULL;
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end if;
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end if;
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-- machine trap setup & handling --
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-- machine trap setup & handling --
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when csr_mstatus_c | csr_misa_c | csr_mie_c | csr_mtvec_c | csr_mcounteren_c | csr_mscratch_c | csr_mepc_c | csr_mcause_c =>
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when csr_mstatus_c | csr_mstatush_c | csr_misa_c | csr_mie_c | csr_mtvec_c | csr_mcounteren_c | csr_mscratch_c | csr_mepc_c | csr_mcause_c =>
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csr_acc_valid <= csr.priv_m_mode; -- M-mode only, NOTE: MISA is read-only in the NEORV32 but we do not cause an exception here for compatibility
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csr_acc_valid <= csr.priv_m_mode; -- M-mode only, NOTE: MISA is read-only in the NEORV32 but we do not cause an exception here for compatibility
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when csr_mip_c | csr_mtval_c => -- NOTE: MIP and MTVAL are read-only in the NEORV32!
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when csr_mip_c | csr_mtval_c => -- NOTE: MIP and MTVAL are read-only in the NEORV32!
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csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only
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csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only
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|
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-- physical memory protection (PMP) - address & configuration --
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-- physical memory protection (PMP) - address & configuration --
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| Line 1353... |
Line 1356... |
when csr_mcountinhibit_c =>
|
when csr_mcountinhibit_c =>
|
csr_acc_valid <= csr.priv_m_mode; -- M-mode only
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csr_acc_valid <= csr.priv_m_mode; -- M-mode only
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|
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-- machine information registers & custom (NEORV32-specific) read-only CSRs --
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-- machine information registers & custom (NEORV32-specific) read-only CSRs --
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when csr_mvendorid_c | csr_marchid_c | csr_mimpid_c | csr_mhartid_c | csr_mzext_c =>
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when csr_mvendorid_c | csr_marchid_c | csr_mimpid_c | csr_mhartid_c | csr_mconfigptr_c | csr_mzext_c =>
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csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only
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csr_acc_valid <= (not csr_wacc_v) and csr.priv_m_mode; -- M-mode only, read-only
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|
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-- debug mode CSRs --
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-- debug mode CSRs --
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when csr_dcsr_c | csr_dpc_c | csr_dscratch0_c =>
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when csr_dcsr_c | csr_dpc_c | csr_dscratch0_c =>
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if (CPU_EXTENSION_RISCV_DEBUG = true) then
|
if (CPU_EXTENSION_RISCV_DEBUG = true) then
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| Line 1373... |
Line 1376... |
end process csr_access_check;
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end process csr_access_check;
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|
|
|
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-- Illegal Instruction Check --------------------------------------------------------------
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-- Illegal Instruction Check --------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
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illegal_instruction_check: process(execute_engine, decode_aux, csr_acc_valid, debug_ctrl)
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illegal_instruction_check: process(execute_engine, decode_aux, csr, csr_acc_valid, debug_ctrl)
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variable opcode_v : std_ulogic_vector(6 downto 0);
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variable opcode_v : std_ulogic_vector(6 downto 0);
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begin
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begin
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-- illegal instructions are checked in the EXECUTE stage
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-- illegal instructions are checked in the EXECUTE stage
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-- the execute engine should not commit any illegal instruction
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-- the execute engine should not commit any illegal instruction
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if (execute_engine.state = EXECUTE) then
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if (execute_engine.state = EXECUTE) then
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| Line 1539... |
Line 1542... |
-- ecall, ebreak, mret, wfi, dret --
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-- ecall, ebreak, mret, wfi, dret --
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elsif (execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c) = "00000") and
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elsif (execute_engine.i_reg(instr_rd_msb_c downto instr_rd_lsb_c) = "00000") and
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(execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c) = "00000") then
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(execute_engine.i_reg(instr_rs1_msb_c downto instr_rs1_lsb_c) = "00000") then
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if (execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_ecall_c) or -- ECALL
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if (execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_ecall_c) or -- ECALL
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(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_ebreak_c) or -- EBREAK
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(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_ebreak_c) or -- EBREAK
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(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_mret_c) or -- MRET
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((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_mret_c)and (CPU_EXTENSION_RISCV_U = true) and (csr.priv_m_mode = '1')) or -- MRET (only allowed in M-mode)
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((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = (funct12_dret_c)) and (CPU_EXTENSION_RISCV_DEBUG = true) and (debug_ctrl.running = '1')) or -- DRET
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((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = (funct12_dret_c)) and (CPU_EXTENSION_RISCV_DEBUG = true) and (debug_ctrl.running = '1')) or -- DRET
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(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_wfi_c) then -- WFI
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((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_wfi_c) and ((csr.priv_m_mode = '1') or (csr.mstatus_tw = '0'))) then -- WFI allowed in M-mode or if mstatus.TW=0
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illegal_instruction <= '0';
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illegal_instruction <= '0';
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else
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else
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illegal_instruction <= '1';
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illegal_instruction <= '1';
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end if;
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end if;
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else
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else
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| Line 1562... |
Line 1565... |
illegal_instruction <= '1';
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illegal_instruction <= '1';
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end if;
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end if;
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when opcode_fop_c => -- floating point operations - single/dual operands
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when opcode_fop_c => -- floating point operations - single/dual operands
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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if (CPU_EXTENSION_RISCV_Zfinx = true) and -- F extension enabled
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if (CPU_EXTENSION_RISCV_Zfinx = true) and (csr.mstatus_fs = '1') and -- F extension implemented and enabled
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(execute_engine.i_reg(instr_funct7_lsb_c+1 downto instr_funct7_lsb_c) = float_single_c) and -- single-precision operations only
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(execute_engine.i_reg(instr_funct7_lsb_c+1 downto instr_funct7_lsb_c) = float_single_c) and -- single-precision operations only
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(decode_aux.is_float_op = '1') then -- is correct/supported floating-point instruction
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(decode_aux.is_float_op = '1') then -- is correct/supported floating-point instruction
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illegal_instruction <= '0';
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illegal_instruction <= '0';
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else
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else
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illegal_instruction <= '1';
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illegal_instruction <= '1';
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| Line 1917... |
Line 1920... |
-- see: https://forums.xilinx.com/t5/General-Technical-Discussion/quot-Don-t-care-quot-reset-value/td-p/412845
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-- see: https://forums.xilinx.com/t5/General-Technical-Discussion/quot-Don-t-care-quot-reset-value/td-p/412845
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if (rstn_i = '0') then
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if (rstn_i = '0') then
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csr.we <= '0';
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csr.we <= '0';
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--
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--
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csr.mstatus_mie <= '0';
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csr.mstatus_mie <= '0';
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csr.mstatus_fs <= '0';
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csr.mstatus_mpie <= '0';
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csr.mstatus_mpie <= '0';
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csr.mstatus_mpp <= (others => '0');
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csr.mstatus_mpp <= (others => '0');
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csr.mstatus_tw <= '0';
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csr.privilege <= priv_mode_m_c; -- start in MACHINE mode
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csr.privilege <= priv_mode_m_c; -- start in MACHINE mode
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csr.mie_msie <= def_rst_val_c;
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csr.mie_msie <= def_rst_val_c;
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csr.mie_meie <= def_rst_val_c;
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csr.mie_meie <= def_rst_val_c;
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csr.mie_mtie <= def_rst_val_c;
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csr.mie_mtie <= def_rst_val_c;
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csr.mie_firqe <= (others => def_rst_val_c);
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csr.mie_firqe <= (others => def_rst_val_c);
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| Line 1991... |
Line 1996... |
csr.mstatus_mie <= csr.wdata(03);
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csr.mstatus_mie <= csr.wdata(03);
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csr.mstatus_mpie <= csr.wdata(07);
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csr.mstatus_mpie <= csr.wdata(07);
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if (CPU_EXTENSION_RISCV_U = true) then -- user mode implemented
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if (CPU_EXTENSION_RISCV_U = true) then -- user mode implemented
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csr.mstatus_mpp(0) <= csr.wdata(11) or csr.wdata(12);
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csr.mstatus_mpp(0) <= csr.wdata(11) or csr.wdata(12);
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csr.mstatus_mpp(1) <= csr.wdata(11) or csr.wdata(12);
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csr.mstatus_mpp(1) <= csr.wdata(11) or csr.wdata(12);
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else -- only machine mode is available
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csr.mstatus_tw <= csr.wdata(21);
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csr.mstatus_mpp <= priv_mode_m_c;
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end if;
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if (CPU_EXTENSION_RISCV_Zfinx = true) then -- FPU implemented
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csr.mstatus_fs <= csr.wdata(14) or csr.wdata(13);
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end if;
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end if;
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end if;
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end if;
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-- R/W: mie - machine interrupt enable register --
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-- R/W: mie - machine interrupt enable register --
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if (csr.addr(3 downto 0) = csr_mie_c(3 downto 0)) then
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if (csr.addr(3 downto 0) = csr_mie_c(3 downto 0)) then
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csr.mie_msie <= csr.wdata(03); -- machine SW IRQ enable
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csr.mie_msie <= csr.wdata(03); -- machine SW IRQ enable
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| Line 2080... |
Line 2087... |
if (csr.addr(4 downto 0) = csr_mcountinhibit_c(4 downto 0)) then
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if (csr.addr(4 downto 0) = csr_mcountinhibit_c(4 downto 0)) then
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csr.mcountinhibit_cy <= csr.wdata(0); -- enable auto-increment of [m]cycle[h] counter
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csr.mcountinhibit_cy <= csr.wdata(0); -- enable auto-increment of [m]cycle[h] counter
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csr.mcountinhibit_ir <= csr.wdata(2); -- enable auto-increment of [m]instret[h] counter
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csr.mcountinhibit_ir <= csr.wdata(2); -- enable auto-increment of [m]instret[h] counter
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csr.mcountinhibit_hpm <= csr.wdata(csr.mcountinhibit_hpm'left+3 downto 3); -- enable auto-increment of [m]hpmcounter*[h] counter
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csr.mcountinhibit_hpm <= csr.wdata(csr.mcountinhibit_hpm'left+3 downto 3); -- enable auto-increment of [m]hpmcounter*[h] counter
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end if;
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end if;
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-- machine performance-monitoring event selector --
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-- machine performance-monitors event selector --
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if (HPM_NUM_CNTS > 0) then
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if (HPM_NUM_CNTS > 0) then
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for i in 0 to HPM_NUM_CNTS-1 loop
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for i in 0 to HPM_NUM_CNTS-1 loop
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if (csr.addr(4 downto 0) = std_ulogic_vector(to_unsigned(i+3, 5))) then
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if (csr.addr(4 downto 0) = std_ulogic_vector(to_unsigned(i+3, 5))) then
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csr.mhpmevent(i) <= csr.wdata(csr.mhpmevent(i)'left downto 0);
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csr.mhpmevent(i) <= csr.wdata(csr.mhpmevent(i)'left downto 0);
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end if;
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end if;
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| Line 2224... |
Line 2231... |
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-- user mode disabled --
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-- user mode disabled --
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if (CPU_EXTENSION_RISCV_U = false) then
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if (CPU_EXTENSION_RISCV_U = false) then
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csr.privilege <= priv_mode_m_c;
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csr.privilege <= priv_mode_m_c;
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csr.mstatus_mpp <= priv_mode_m_c;
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csr.mstatus_mpp <= priv_mode_m_c;
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csr.mstatus_tw <= '0';
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csr.mcounteren_cy <= '0';
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csr.mcounteren_cy <= '0';
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csr.mcounteren_tm <= '0';
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csr.mcounteren_tm <= '0';
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csr.mcounteren_ir <= '0';
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csr.mcounteren_ir <= '0';
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csr.dcsr_ebreaku <= '0';
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csr.dcsr_ebreaku <= '0';
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csr.dcsr_prv <= priv_mode_m_c;
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csr.dcsr_prv <= priv_mode_m_c;
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| Line 2253... |
Line 2261... |
csr.mcountinhibit_ir <= '0';
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csr.mcountinhibit_ir <= '0';
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end if;
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end if;
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-- floating-point extension disabled --
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-- floating-point extension disabled --
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if (CPU_EXTENSION_RISCV_Zfinx = false) then
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if (CPU_EXTENSION_RISCV_Zfinx = false) then
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csr.mstatus_fs <= '0';
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csr.fflags <= (others => '0');
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csr.fflags <= (others => '0');
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csr.frm <= (others => '0');
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csr.frm <= (others => '0');
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end if;
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end if;
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-- debug mode disabled --
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-- debug mode disabled --
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| Line 2500... |
Line 2509... |
when csr_mstatus_c => -- mstatus (r/w): machine status register
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when csr_mstatus_c => -- mstatus (r/w): machine status register
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csr.rdata(03) <= csr.mstatus_mie; -- MIE
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csr.rdata(03) <= csr.mstatus_mie; -- MIE
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csr.rdata(07) <= csr.mstatus_mpie; -- MPIE
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csr.rdata(07) <= csr.mstatus_mpie; -- MPIE
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csr.rdata(11) <= csr.mstatus_mpp(0); -- MPP: machine previous privilege mode low
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csr.rdata(11) <= csr.mstatus_mpp(0); -- MPP: machine previous privilege mode low
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csr.rdata(12) <= csr.mstatus_mpp(1); -- MPP: machine previous privilege mode high
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csr.rdata(12) <= csr.mstatus_mpp(1); -- MPP: machine previous privilege mode high
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csr.rdata(13) <= csr.mstatus_fs; -- FS(0): FPU status - OFF or DIRTY
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csr.rdata(14) <= csr.mstatus_fs; -- FS(1): FPU status - OFF or DIRTY
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csr.rdata(21) <= csr.mstatus_tw; -- TW: WFI timeout wait
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csr.rdata(31) <= csr.mstatus_fs; -- SD: state dirty (only FPU yet)
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when csr_misa_c => -- misa (r/-): ISA and extensions
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when csr_misa_c => -- misa (r/-): ISA and extensions
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csr.rdata(00) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_A); -- A CPU extension
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csr.rdata(00) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_A); -- A CPU extension
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csr.rdata(02) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_C); -- C CPU extension
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csr.rdata(02) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_C); -- C CPU extension
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csr.rdata(04) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- E CPU extension
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csr.rdata(04) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- E CPU extension
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csr.rdata(08) <= not bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- I CPU extension (if not E)
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csr.rdata(08) <= not bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- I CPU extension (if not E)
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| Line 2537... |
Line 2550... |
when csr_mepc_c => -- mepc (r/w): machine exception program counter
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when csr_mepc_c => -- mepc (r/w): machine exception program counter
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csr.rdata <= csr.mepc(data_width_c-1 downto 1) & '0';
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csr.rdata <= csr.mepc(data_width_c-1 downto 1) & '0';
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when csr_mcause_c => -- mcause (r/w): machine trap cause
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when csr_mcause_c => -- mcause (r/w): machine trap cause
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csr.rdata(31) <= csr.mcause(csr.mcause'left);
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csr.rdata(31) <= csr.mcause(csr.mcause'left);
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csr.rdata(csr.mcause'left-1 downto 0) <= csr.mcause(csr.mcause'left-1 downto 0);
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csr.rdata(csr.mcause'left-1 downto 0) <= csr.mcause(csr.mcause'left-1 downto 0);
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when csr_mtval_c => -- mtval (r/w): machine bad address or instruction
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when csr_mtval_c => -- mtval (r/-): machine bad address or instruction
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csr.rdata <= csr.mtval;
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csr.rdata <= csr.mtval;
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when csr_mip_c => -- mip (r/-): machine interrupt pending
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when csr_mip_c => -- mip (r/-): machine interrupt pending
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csr.rdata(03) <= trap_ctrl.irq_buf(interrupt_msw_irq_c);
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csr.rdata(03) <= trap_ctrl.irq_buf(interrupt_msw_irq_c);
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csr.rdata(07) <= trap_ctrl.irq_buf(interrupt_mtime_irq_c);
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csr.rdata(07) <= trap_ctrl.irq_buf(interrupt_mtime_irq_c);
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csr.rdata(11) <= trap_ctrl.irq_buf(interrupt_mext_irq_c);
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csr.rdata(11) <= trap_ctrl.irq_buf(interrupt_mext_irq_c);
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| Line 2755... |
Line 2768... |
-- --------------------------------------------------------------------
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-- --------------------------------------------------------------------
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-- when csr_mvendorid_c => csr.rdata <= (others => '0'); -- mvendorid (r/-): vendor ID, implemented but always zero
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-- when csr_mvendorid_c => csr.rdata <= (others => '0'); -- mvendorid (r/-): vendor ID, implemented but always zero
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when csr_marchid_c => csr.rdata(4 downto 0) <= "10011"; -- marchid (r/-): arch ID - official RISC-V open-source arch ID
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when csr_marchid_c => csr.rdata(4 downto 0) <= "10011"; -- marchid (r/-): arch ID - official RISC-V open-source arch ID
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when csr_mimpid_c => csr.rdata <= hw_version_c; -- mimpid (r/-): implementation ID -- NEORV32 hardware version
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when csr_mimpid_c => csr.rdata <= hw_version_c; -- mimpid (r/-): implementation ID -- NEORV32 hardware version
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when csr_mhartid_c => csr.rdata <= std_ulogic_vector(to_unsigned(HW_THREAD_ID, 32)); -- mhartid (r/-): hardware thread ID
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when csr_mhartid_c => csr.rdata <= std_ulogic_vector(to_unsigned(HW_THREAD_ID, 32)); -- mhartid (r/-): hardware thread ID
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-- when csr_mconfigptr_c => csr.rdata <= (others => '0'); -- mconfigptr (r/-): machine configuration pointer register, implemented but not assigned yet
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-- custom machine read-only CSRs --
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-- custom machine read-only CSRs --
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-- --------------------------------------------------------------------
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-- --------------------------------------------------------------------
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when csr_mzext_c => -- mzext (r/-): available RISC-V Z* sub-extensions
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when csr_mzext_c => -- mzext (r/-): available RISC-V Z* sub-extensions
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csr.rdata(0) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr); -- Zicsr
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csr.rdata(0) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr); -- Zicsr
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