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Line 7... |
-- # handling controller and the RISC-V status and control register set (CSRs) including the #
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-- # handling controller and the RISC-V status and control register set (CSRs) including the #
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-- # hardware performance monitor counters. #
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-- # hardware performance monitor counters. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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| Line 393... |
Line 393... |
fetch_engine.pc <= (others => def_rst_val_c);
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fetch_engine.pc <= (others => def_rst_val_c);
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elsif rising_edge(clk_i) then
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elsif rising_edge(clk_i) then
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fetch_engine.state <= fetch_engine.state_nxt;
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fetch_engine.state <= fetch_engine.state_nxt;
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fetch_engine.state_prev <= fetch_engine.state;
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fetch_engine.state_prev <= fetch_engine.state;
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fetch_engine.restart <= fetch_engine.restart_nxt or fetch_engine.reset;
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fetch_engine.restart <= fetch_engine.restart_nxt or fetch_engine.reset;
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if (fetch_engine.restart = '1') then
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if (fetch_engine.restart = '1') and (fetch_engine.state = IFETCH_REQUEST) then -- only update PC if no fetch request is pending
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fetch_engine.pc <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- initialize with "real" application PC
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fetch_engine.pc <= execute_engine.pc(data_width_c-1 downto 1) & '0'; -- initialize with "real" application PC
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else
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else
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fetch_engine.pc <= fetch_engine.pc_nxt;
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fetch_engine.pc <= fetch_engine.pc_nxt;
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end if;
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end if;
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end if;
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end if;
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Line 419... |
fetch_engine.restart_nxt <= fetch_engine.restart;
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fetch_engine.restart_nxt <= fetch_engine.restart;
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-- instruction prefetch buffer defaults --
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-- instruction prefetch buffer defaults --
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ipb.we <= '0';
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ipb.we <= '0';
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ipb.wdata <= be_instr_i & ma_instr_i & instr_i(31 downto 0); -- store exception info and instruction word
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ipb.wdata <= be_instr_i & ma_instr_i & instr_i(31 downto 0); -- store exception info and instruction word
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ipb.clear <= fetch_engine.restart;
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ipb.clear <= fetch_engine.restart; -- clear instruction buffer while being reset
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-- state machine --
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-- state machine --
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case fetch_engine.state is
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case fetch_engine.state is
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when IFETCH_REQUEST => -- request new 32-bit-aligned instruction word
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when IFETCH_REQUEST => -- request new 32-bit-aligned instruction word
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Line 438... |
-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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fetch_engine.bus_err_ack <= be_instr_i or ma_instr_i; -- ACK bus/alignment errors
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fetch_engine.bus_err_ack <= be_instr_i or ma_instr_i; -- ACK bus/alignment errors
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if (bus_i_wait_i = '0') or (be_instr_i = '1') or (ma_instr_i = '1') then -- wait for bus response
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if (bus_i_wait_i = '0') or (be_instr_i = '1') or (ma_instr_i = '1') then -- wait for bus response
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fetch_engine.pc_nxt <= std_ulogic_vector(unsigned(fetch_engine.pc) + 4);
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fetch_engine.pc_nxt <= std_ulogic_vector(unsigned(fetch_engine.pc) + 4);
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ipb.we <= not fetch_engine.restart; -- write to IPB if not being reset
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ipb.we <= not fetch_engine.restart; -- write to IPB if not being reset
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fetch_engine.restart_nxt <= '0';
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fetch_engine.state_nxt <= IFETCH_REQUEST;
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fetch_engine.state_nxt <= IFETCH_REQUEST;
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end if;
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end if;
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when others => -- undefined
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when others => -- undefined
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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Line 722... |
if (execute_engine.state = EXECUTE) then
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if (execute_engine.state = EXECUTE) then
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execute_engine.last_pc <= execute_engine.pc;
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execute_engine.last_pc <= execute_engine.pc;
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execute_engine.i_reg_last <= execute_engine.i_reg;
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execute_engine.i_reg_last <= execute_engine.i_reg;
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end if;
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end if;
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-- next PC --
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-- next PC logic --
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case execute_engine.state is
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case execute_engine.state is
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when TRAP_ENTER => -- ENTERING trap environment
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when TRAP_ENTER => -- ENTERING trap environment
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if (CPU_EXTENSION_RISCV_DEBUG = false) then -- normal trapping
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if (CPU_EXTENSION_RISCV_DEBUG = false) then -- normal trapping
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execute_engine.next_pc <= csr.mtvec(data_width_c-1 downto 1) & '0'; -- trap enter
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execute_engine.next_pc <= csr.mtvec(data_width_c-1 downto 1) & '0'; -- trap enter
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else -- DEBUG MODE enabled
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else -- DEBUG MODE enabled
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Line 2402... |
end if;
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end if;
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end process hpmcnt_ctrl;
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end process hpmcnt_ctrl;
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-- counter event trigger - RISC-V-specific --
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-- counter event trigger - RISC-V-specific --
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cnt_event(hpmcnt_event_cy_c) <= not execute_engine.sleep; -- active cycle
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cnt_event(hpmcnt_event_cy_c) <= not execute_engine.sleep; -- active cycle
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cnt_event(hpmcnt_event_never_c) <= '0'; -- undefined (never)
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cnt_event(hpmcnt_event_never_c) <= '0'; -- "never"
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cnt_event(hpmcnt_event_ir_c) <= '1' when (execute_engine.state = EXECUTE) else '0'; -- retired instruction
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cnt_event(hpmcnt_event_ir_c) <= '1' when (execute_engine.state = EXECUTE) else '0'; -- (any) retired instruction
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-- counter event trigger - custom / NEORV32-specific --
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-- counter event trigger - custom / NEORV32-specific --
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cnt_event(hpmcnt_event_cir_c) <= '1' when (execute_engine.state = EXECUTE) and (execute_engine.is_ci = '1') else '0'; -- retired compressed instruction
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cnt_event(hpmcnt_event_cir_c) <= '1' when (execute_engine.state = EXECUTE) and (execute_engine.is_ci = '1') else '0'; -- retired compressed instruction
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cnt_event(hpmcnt_event_wait_if_c) <= '1' when (fetch_engine.state = IFETCH_ISSUE) and (fetch_engine.state_prev = IFETCH_ISSUE) else '0'; -- instruction fetch memory wait cycle
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cnt_event(hpmcnt_event_wait_if_c) <= '1' when (fetch_engine.state = IFETCH_ISSUE) and (fetch_engine.state_prev = IFETCH_ISSUE) else '0'; -- instruction fetch memory wait cycle
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cnt_event(hpmcnt_event_wait_ii_c) <= '1' when (execute_engine.state = DISPATCH) and (execute_engine.state_prev = DISPATCH) else '0'; -- instruction issue wait cycle
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cnt_event(hpmcnt_event_wait_ii_c) <= '1' when (execute_engine.state = DISPATCH) and (execute_engine.state_prev = DISPATCH) else '0'; -- instruction issue wait cycle
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