| Line 1... |
Line 1... |
-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - CPU Control >> #
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-- # << NEORV32 - CPU Operations Control Unit >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # CPU operation is split into a fetch engine (responsible for fetching instruction data), an #
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-- # CPU operations are controlled by several "engines" (modules). These engines operate in #
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-- # issue engine (for recoding compressed instructions and for constructing 32-bit instruction #
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-- # parallel to implement a simple pipeline: #
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-- # words) and an execute engine (responsible for actually executing the instructions), a trap #
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-- # + Fetch engine: Fetches 32-bit chunks of instruction words #
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-- # handling controller and the RISC-V status and control register set (CSRs) including the #
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-- # + Issue engine: Decodes compressed instructions, aligns and queues instruction words #
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-- # hardware performance monitor counters. #
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-- # + Execute engine: Multi-cycle execution of instructions (generate control signals) #
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-- # + Trap engine: Handles interrupts and exceptions #
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-- # + CSR module: Read/write accesses to CSRs & HW counters #
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-- # + Debug module: CPU debug mode handling (on-chip debugger) #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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| Line 164... |
Line 167... |
signal ci_instr16 : std_ulogic_vector(15 downto 0);
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signal ci_instr16 : std_ulogic_vector(15 downto 0);
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signal ci_instr32 : std_ulogic_vector(31 downto 0);
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signal ci_instr32 : std_ulogic_vector(31 downto 0);
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signal ci_illegal : std_ulogic;
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signal ci_illegal : std_ulogic;
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-- instruction issue engine --
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-- instruction issue engine --
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type issue_engine_state_t is (ISSUE_ACTIVE, ISSUE_REALIGN);
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type issue_engine_t is record
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type issue_engine_t is record
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state : issue_engine_state_t;
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realign : std_ulogic;
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state_nxt : issue_engine_state_t;
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realign_nxt : std_ulogic;
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align : std_ulogic;
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align : std_ulogic;
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align_nxt : std_ulogic;
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align_nxt : std_ulogic;
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buf : std_ulogic_vector(2+15 downto 0);
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buf : std_ulogic_vector(2+15 downto 0);
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buf_nxt : std_ulogic_vector(2+15 downto 0);
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buf_nxt : std_ulogic_vector(2+15 downto 0);
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end record;
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end record;
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| Line 184... |
Line 186... |
end record;
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end record;
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signal cmd_issue : cmd_issue_t;
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signal cmd_issue : cmd_issue_t;
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|
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-- instruction decoding helper logic --
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-- instruction decoding helper logic --
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type decode_aux_t is record
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type decode_aux_t is record
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is_atomic_lr : std_ulogic;
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is_a_lr : std_ulogic;
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is_atomic_sc : std_ulogic;
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is_a_sc : std_ulogic;
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is_float_op : std_ulogic;
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is_f_op : std_ulogic;
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sys_env_cmd : std_ulogic_vector(11 downto 0);
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sys_env_cmd : std_ulogic_vector(11 downto 0);
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is_m_mul : std_ulogic;
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is_m_mul : std_ulogic;
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is_m_div : std_ulogic;
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is_m_div : std_ulogic;
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is_bitmanip_imm : std_ulogic;
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is_b_imm : std_ulogic;
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is_bitmanip_reg : std_ulogic;
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is_b_reg : std_ulogic;
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rs1_zero : std_ulogic;
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rs1_zero : std_ulogic;
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rs2_zero : std_ulogic;
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rs2_zero : std_ulogic;
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rd_zero : std_ulogic;
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rd_zero : std_ulogic;
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end record;
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end record;
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signal decode_aux : decode_aux_t;
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signal decode_aux : decode_aux_t;
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| Line 236... |
Line 238... |
type trap_ctrl_t is record
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type trap_ctrl_t is record
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exc_buf : std_ulogic_vector(exception_width_c-1 downto 0);
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exc_buf : std_ulogic_vector(exception_width_c-1 downto 0);
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exc_fire : std_ulogic; -- set if there is a valid source in the exception buffer
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exc_fire : std_ulogic; -- set if there is a valid source in the exception buffer
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irq_buf : std_ulogic_vector(interrupt_width_c-1 downto 0);
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irq_buf : std_ulogic_vector(interrupt_width_c-1 downto 0);
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irq_fire : std_ulogic; -- set if there is a valid source in the interrupt buffer
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irq_fire : std_ulogic; -- set if there is a valid source in the interrupt buffer
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exc_ack : std_ulogic; -- acknowledge all exceptions
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exc_clr : std_ulogic; -- clear all buffered exceptions
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cause : std_ulogic_vector(6 downto 0); -- trap ID for mcause CSR
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cause : std_ulogic_vector(6 downto 0); -- trap ID for mcause CSR
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cause_nxt : std_ulogic_vector(6 downto 0);
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cause_nxt : std_ulogic_vector(6 downto 0);
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db_irq_fire : std_ulogic; -- set if there is a valid IRQ source in the "enter debug mode" trap buffer
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db_irq_fire : std_ulogic; -- set if there is a valid IRQ source in the "enter debug mode" trap buffer
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db_irq_en : std_ulogic; -- set if IRQs are allowed in debug mode
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db_irq_en : std_ulogic; -- set if IRQs are allowed in debug mode
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--
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--
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| Line 249... |
Line 251... |
env_end : std_ulogic; -- end trap handler env
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env_end : std_ulogic; -- end trap handler env
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--
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--
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instr_be : std_ulogic; -- instruction fetch bus error
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instr_be : std_ulogic; -- instruction fetch bus error
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instr_ma : std_ulogic; -- instruction fetch misaligned address
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instr_ma : std_ulogic; -- instruction fetch misaligned address
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instr_il : std_ulogic; -- illegal instruction
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instr_il : std_ulogic; -- illegal instruction
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env_call : std_ulogic;
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env_call : std_ulogic; -- ecall instruction
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break_point : std_ulogic;
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break_point : std_ulogic; -- ebreak instruction
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end record;
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end record;
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signal trap_ctrl : trap_ctrl_t;
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signal trap_ctrl : trap_ctrl_t;
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-- CPU main control bus --
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-- CPU main control bus --
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signal ctrl_nxt, ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0);
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signal ctrl_nxt, ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0);
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| Line 422... |
Line 424... |
ipb.we <= '0';
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ipb.we <= '0';
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ipb.wdata <= be_instr_i & ma_instr_i & instr_i(31 downto 0); -- store exception info and instruction word
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ipb.wdata <= be_instr_i & ma_instr_i & instr_i(31 downto 0); -- store exception info and instruction word
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ipb.clear <= fetch_engine.restart; -- clear instruction buffer while being reset
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ipb.clear <= fetch_engine.restart; -- clear instruction buffer while being reset
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-- state machine --
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-- state machine --
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case fetch_engine.state is
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if (fetch_engine.state = IFETCH_REQUEST) then -- IFETCH_REQUEST: request new 32-bit-aligned instruction word
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when IFETCH_REQUEST => -- request new 32-bit-aligned instruction word
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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if (ipb.free = '1') and (fetch_engine.restart = '0') then -- free entry in buffer AND no reset request?
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if (ipb.free = '1') and (fetch_engine.restart = '0') then -- free entry in buffer AND no reset request?
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bus_fast_ir <= '1'; -- fast instruction fetch request
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bus_fast_ir <= '1'; -- fast instruction fetch request
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fetch_engine.state_nxt <= IFETCH_ISSUE;
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fetch_engine.state_nxt <= IFETCH_ISSUE;
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end if;
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end if;
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fetch_engine.restart_nxt <= '0';
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fetch_engine.restart_nxt <= '0';
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when IFETCH_ISSUE => -- store instruction data to prefetch buffer
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else -- IFETCH_ISSUE: store instruction data to prefetch buffer
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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fetch_engine.bus_err_ack <= be_instr_i or ma_instr_i; -- ACK bus/alignment errors
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fetch_engine.bus_err_ack <= be_instr_i or ma_instr_i; -- ACK bus/alignment errors
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if (bus_i_wait_i = '0') or (be_instr_i = '1') or (ma_instr_i = '1') then -- wait for bus response
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if (bus_i_wait_i = '0') or (be_instr_i = '1') or (ma_instr_i = '1') then -- wait for bus response
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fetch_engine.pc_nxt <= std_ulogic_vector(unsigned(fetch_engine.pc) + 4);
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fetch_engine.pc_nxt <= std_ulogic_vector(unsigned(fetch_engine.pc) + 4);
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ipb.we <= not fetch_engine.restart; -- write to IPB if not being reset
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ipb.we <= not fetch_engine.restart; -- write to IPB if not being reset
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fetch_engine.state_nxt <= IFETCH_REQUEST;
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fetch_engine.state_nxt <= IFETCH_REQUEST;
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end if;
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end if;
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when others => -- undefined
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end if;
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-- ------------------------------------------------------------
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fetch_engine.state_nxt <= IFETCH_REQUEST;
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end case;
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end process fetch_engine_fsm_comb;
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end process fetch_engine_fsm_comb;
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-- ****************************************************************************************************************************
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-- ****************************************************************************************************************************
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-- Instruction Prefetch Buffer
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-- Instruction Prefetch Buffer
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| Line 488... |
Line 484... |
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-- Issue Engine FSM Sync ------------------------------------------------------------------
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-- Issue Engine FSM Sync ------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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issue_engine_fsm_sync: process(rstn_i, clk_i)
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issue_engine_fsm_sync: process(rstn_i, clk_i)
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begin
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begin
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if (rstn_i = '0') then
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if (rstn_i = '0') then -- always start aligned after reset
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issue_engine.state <= ISSUE_ACTIVE;
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issue_engine.align <= '0';
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issue_engine.align <= CPU_BOOT_ADDR(1); -- 32- or 16-bit boundary
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issue_engine.realign <= '0';
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issue_engine.buf <= (others => '0');
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issue_engine.buf <= (others => def_rst_val_c);
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elsif rising_edge(clk_i) then
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elsif rising_edge(clk_i) then
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if (ipb.clear = '1') then
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if (ipb.clear = '1') then
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if (CPU_EXTENSION_RISCV_C = true) and (execute_engine.pc(1) = '1') then -- branch to unaligned address?
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if (CPU_EXTENSION_RISCV_C = true) and (execute_engine.pc(1) = '1') then -- branch to unaligned address?
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issue_engine.state <= ISSUE_REALIGN;
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issue_engine.align <= '1'; -- aligned on 16-bit boundary
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issue_engine.align <= '1'; -- aligned on 16-bit boundary
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issue_engine.realign <= '1';
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else
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else
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issue_engine.state <= issue_engine.state_nxt;
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issue_engine.align <= '0'; -- aligned on 32-bit boundary
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issue_engine.align <= '0'; -- aligned on 32-bit boundary
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issue_engine.realign <= '0';
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end if;
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end if;
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else
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else
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issue_engine.state <= issue_engine.state_nxt;
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issue_engine.align <= issue_engine.align_nxt;
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issue_engine.align <= issue_engine.align_nxt;
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issue_engine.realign <= issue_engine.realign_nxt;
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end if;
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end if;
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issue_engine.buf <= issue_engine.buf_nxt;
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issue_engine.buf <= issue_engine.buf_nxt;
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end if;
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end if;
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end process issue_engine_fsm_sync;
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end process issue_engine_fsm_sync;
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| Line 515... |
Line 511... |
-- Issue Engine FSM Comb ------------------------------------------------------------------
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-- Issue Engine FSM Comb ------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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issue_engine_fsm_comb: process(issue_engine, ipb, execute_engine, ci_illegal, ci_instr32)
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issue_engine_fsm_comb: process(issue_engine, ipb, execute_engine, ci_illegal, ci_instr32)
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begin
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begin
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-- arbiter defaults --
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-- arbiter defaults --
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issue_engine.state_nxt <= issue_engine.state;
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issue_engine.realign_nxt <= issue_engine.realign;
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issue_engine.align_nxt <= issue_engine.align;
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issue_engine.align_nxt <= issue_engine.align;
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issue_engine.buf_nxt <= issue_engine.buf;
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issue_engine.buf_nxt <= issue_engine.buf;
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-- instruction prefetch buffer interface defaults --
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-- instruction prefetch buffer interface defaults --
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ipb.re <= '0';
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ipb.re <= '0';
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-- instruction issue interface defaults --
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-- instruction issue interface defaults --
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cmd_issue.valid <= '0';
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-- construct instruction data --
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-- cmd_issue.data = <illegal_compressed_instruction> & <bus_error & alignment_error> & <is_compressed_instrucion> & <32-bit_instruction_word>
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-- cmd_issue.data = <illegal_compressed_instruction> & <bus_error & alignment_error> & <is_compressed_instrucion> & <32-bit_instruction_word>
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if (issue_engine.align = '0') or (CPU_EXTENSION_RISCV_C = false) then -- 32-bit aligned
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if (ipb.rdata(1 downto 0) = "11") or (CPU_EXTENSION_RISCV_C = false) then -- uncompressed
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cmd_issue.data <= '0' & ipb.rdata(33 downto 32) & '0' & ipb.rdata(31 downto 0);
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cmd_issue.data <= '0' & ipb.rdata(33 downto 32) & '0' & ipb.rdata(31 downto 0);
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cmd_issue.valid <= '0';
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else -- compressed
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cmd_issue.data <= ci_illegal & ipb.rdata(33 downto 32) & '1' & ci_instr32;
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end if;
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else -- not 32-bit aligned
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if (issue_engine.buf(1 downto 0) = "11") then -- uncompressed
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cmd_issue.data <= '0' & (ipb.rdata(33 downto 32) or issue_engine.buf(17 downto 16)) & '0' & (ipb.rdata(15 downto 0) & issue_engine.buf(15 downto 0));
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else -- compressed
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cmd_issue.data <= ci_illegal & ipb.rdata(33 downto 32) & '1' & ci_instr32;
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end if;
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end if;
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|
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-- store high half-word - we might need it for an unaligned uncompressed instruction --
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if (execute_engine.state = DISPATCH) and (ipb.avail = '1') and (CPU_EXTENSION_RISCV_C = true) then
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issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16);
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end if;
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|
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|
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-- state machine --
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-- state machine --
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case issue_engine.state is
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if (ipb.avail = '1') then -- instruction data available?
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|
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when ISSUE_ACTIVE => -- issue instruction if available
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if (issue_engine.realign = '0') then -- issue instruction if available
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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if (ipb.avail = '1') then -- instructions available?
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cmd_issue.valid <= '1';
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|
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if (issue_engine.align = '0') or (CPU_EXTENSION_RISCV_C = false) then -- begin check in LOW instruction half-word
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if (issue_engine.align = '0') or (CPU_EXTENSION_RISCV_C = false) then -- begin check in LOW instruction half-word
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if (execute_engine.state = DISPATCH) then -- ready to issue new command?
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if (execute_engine.state = DISPATCH) then -- ready to issue new command?
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ipb.re <= '1';
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ipb.re <= '1';
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cmd_issue.valid <= '1';
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if (ipb.rdata(1 downto 0) /= "11") and (CPU_EXTENSION_RISCV_C = true) then -- compressed
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issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16); -- store high half-word - we might need it for an unaligned uncompressed instruction
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if (ipb.rdata(1 downto 0) = "11") or (CPU_EXTENSION_RISCV_C = false) then -- uncompressed and "aligned"
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cmd_issue.data <= '0' & ipb.rdata(33 downto 32) & '0' & ipb.rdata(31 downto 0);
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else -- compressed
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cmd_issue.data <= ci_illegal & ipb.rdata(33 downto 32) & '1' & ci_instr32;
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issue_engine.align_nxt <= '1';
|
issue_engine.align_nxt <= '1';
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end if;
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end if;
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end if;
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end if;
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|
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else -- begin check in HIGH instruction half-word
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else -- begin check in HIGH instruction half-word
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if (execute_engine.state = DISPATCH) then -- ready to issue new command?
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if (execute_engine.state = DISPATCH) then -- ready to issue new command?
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cmd_issue.valid <= '1';
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if (issue_engine.buf(1 downto 0) = "11") then -- uncompressed and unaligned
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issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16); -- store high half-word - we might need it for an unaligned uncompressed instruction
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if (issue_engine.buf(1 downto 0) = "11") then -- uncompressed and "unaligned"
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ipb.re <= '1';
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ipb.re <= '1';
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cmd_issue.data <= '0' & (ipb.rdata(33 downto 32) or issue_engine.buf(17 downto 16)) & '0' & (ipb.rdata(15 downto 0) & issue_engine.buf(15 downto 0));
|
else -- compressed - do not read from ipb here!
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else -- compressed
|
|
-- do not read from ipb here!
|
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cmd_issue.data <= ci_illegal & ipb.rdata(33 downto 32) & '1' & ci_instr32;
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issue_engine.align_nxt <= '0';
|
issue_engine.align_nxt <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
|
when ISSUE_REALIGN => -- re-align input fifos after a branch to an unaligned address
|
else -- re-align input fifo and half-word buffer after a branch to an unaligned address
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
issue_engine.buf_nxt <= ipb.rdata(33 downto 32) & ipb.rdata(31 downto 16);
|
|
if (ipb.avail = '1') then -- instructions available?
|
|
ipb.re <= '1';
|
ipb.re <= '1';
|
issue_engine.state_nxt <= ISSUE_ACTIVE;
|
issue_engine.realign_nxt <= '0';
|
end if;
|
end if;
|
|
|
when others => -- undefined
|
end if;
|
-- ------------------------------------------------------------
|
|
issue_engine.state_nxt <= ISSUE_ACTIVE;
|
|
|
|
end case;
|
|
end process issue_engine_fsm_comb;
|
end process issue_engine_fsm_comb;
|
|
|
-- 16-bit instructions: half-word select --
|
-- 16-bit instructions: half-word select --
|
ci_instr16 <= ipb.rdata(15 downto 0) when (issue_engine.align = '0') else issue_engine.buf(15 downto 0);
|
ci_instr16 <= ipb.rdata(15 downto 0) when (issue_engine.align = '0') else issue_engine.buf(15 downto 0);
|
|
|
| Line 669... |
Line 668... |
execute_engine.branch_taken <= cmp_i(cmp_equal_c);
|
execute_engine.branch_taken <= cmp_i(cmp_equal_c);
|
when funct3_bne_c => -- branch if not equal
|
when funct3_bne_c => -- branch if not equal
|
execute_engine.branch_taken <= not cmp_i(cmp_equal_c);
|
execute_engine.branch_taken <= not cmp_i(cmp_equal_c);
|
when funct3_blt_c | funct3_bltu_c => -- branch if less (signed/unsigned)
|
when funct3_blt_c | funct3_bltu_c => -- branch if less (signed/unsigned)
|
execute_engine.branch_taken <= cmp_i(cmp_less_c);
|
execute_engine.branch_taken <= cmp_i(cmp_less_c);
|
when funct3_bge_c | funct3_bgeu_c => -- branch if greater or equal (signed/unsigned)
|
when others => -- branch if greater or equal (signed/unsigned), invalid funct3 are checked by illegal instr. logic
|
execute_engine.branch_taken <= not cmp_i(cmp_less_c);
|
execute_engine.branch_taken <= not cmp_i(cmp_less_c);
|
when others => -- invalid
|
|
execute_engine.branch_taken <= '0';
|
|
end case;
|
end case;
|
end process branch_check;
|
end process branch_check;
|
|
|
|
|
-- Execute Engine FSM Sync ----------------------------------------------------------------
|
-- Execute Engine FSM Sync ----------------------------------------------------------------
|
| Line 811... |
Line 808... |
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
decode_helper: process(execute_engine)
|
decode_helper: process(execute_engine)
|
variable sys_env_cmd_mask_v : std_ulogic_vector(11 downto 0);
|
variable sys_env_cmd_mask_v : std_ulogic_vector(11 downto 0);
|
begin
|
begin
|
-- defaults --
|
-- defaults --
|
decode_aux.is_atomic_lr <= '0';
|
decode_aux.is_a_lr <= '0';
|
decode_aux.is_atomic_sc <= '0';
|
decode_aux.is_a_sc <= '0';
|
decode_aux.is_float_op <= '0';
|
decode_aux.is_f_op <= '0';
|
decode_aux.is_m_mul <= '0';
|
decode_aux.is_m_mul <= '0';
|
decode_aux.is_m_div <= '0';
|
decode_aux.is_m_div <= '0';
|
decode_aux.is_bitmanip_imm <= '0';
|
decode_aux.is_b_imm <= '0';
|
decode_aux.is_bitmanip_reg <= '0';
|
decode_aux.is_b_reg <= '0';
|
decode_aux.rs1_zero <= '0';
|
decode_aux.rs1_zero <= '0';
|
decode_aux.rs2_zero <= '0';
|
decode_aux.rs2_zero <= '0';
|
decode_aux.rd_zero <= '0';
|
decode_aux.rd_zero <= '0';
|
|
|
-- is atomic load-reservate/store-conditional? --
|
-- is atomic load-reservate/store-conditional? --
|
if (CPU_EXTENSION_RISCV_A = true) and (execute_engine.i_reg(instr_opcode_lsb_c+2) = '1') then -- valid atomic sub-opcode
|
if (CPU_EXTENSION_RISCV_A = true) and (execute_engine.i_reg(instr_opcode_lsb_c+2) = '1') then -- valid atomic sub-opcode
|
decode_aux.is_atomic_lr <= not execute_engine.i_reg(instr_funct5_lsb_c);
|
decode_aux.is_a_lr <= not execute_engine.i_reg(instr_funct5_lsb_c);
|
decode_aux.is_atomic_sc <= execute_engine.i_reg(instr_funct5_lsb_c);
|
decode_aux.is_a_sc <= execute_engine.i_reg(instr_funct5_lsb_c);
|
end if;
|
end if;
|
|
|
-- is BITMANIP instruction? --
|
-- is BITMANIP instruction? --
|
-- pretty complex as we have to extract this from the ALU/ALUI instruction space --
|
-- pretty complex as we have to extract this from the ALU/ALUI instruction space --
|
-- immediate operation --
|
-- immediate operation --
|
| Line 842... |
Line 839... |
(execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00101") -- SEXT.H
|
(execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00101") -- SEXT.H
|
)
|
)
|
) or
|
) or
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110000") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101")) or -- RORI
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110000") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101")) or -- RORI
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0010100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101") and (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00111")) or -- ORCB
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0010100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101") and (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "00111")) or -- ORCB
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101") and (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c) = "11000")) then -- REV8
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101")) or -- REV8
|
decode_aux.is_bitmanip_imm <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_B); -- BITMANIP implemented at all?
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0100100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- BCLRI
|
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0100100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101")) or -- BEXTI
|
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- BINVI
|
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0010100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) then -- BSETI
|
|
decode_aux.is_b_imm <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_B); -- BITMANIP implemented at all?
|
end if;
|
end if;
|
-- register operation --
|
-- register operation --
|
if ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110000") and (execute_engine.i_reg(instr_funct3_msb_c-1 downto instr_funct3_lsb_c) = "01")) or -- ROR / ROL
|
if ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110000") and (execute_engine.i_reg(instr_funct3_msb_c-1 downto instr_funct3_lsb_c) = "01")) or -- ROR / ROL
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000101") and (execute_engine.i_reg(instr_funct3_msb_c) = '1')) or -- MIN[U] / MAX[U]
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000101") and (execute_engine.i_reg(instr_funct3_msb_c) = '1')) or -- MIN[U] / MAX[U]
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "100")) or -- ZEXTH
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "100")) or -- ZEXTH
|
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0100100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- BCLR
|
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0100100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "101")) or -- BEXT
|
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0110100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- BINV
|
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0010100") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- BSET
|
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000101") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "001")) or -- CLMUL
|
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000101") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "011")) or -- CLMULH
|
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000101") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "010")) or -- CLMULR
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0100000") and
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0100000") and
|
(
|
(
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "111") or -- ANDN
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "111") or -- ANDN
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "110") or -- ORN
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "110") or -- ORN
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "100") -- XORN
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "100") -- XORN
|
| Line 863... |
Line 871... |
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "010") or -- SH1ADD
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "010") or -- SH1ADD
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "100") or -- SH2ADD
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "100") or -- SH2ADD
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "110") -- SH3ADD
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "110") -- SH3ADD
|
)
|
)
|
) then
|
) then
|
decode_aux.is_bitmanip_reg <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_B); -- BITMANIP implemented at all?
|
decode_aux.is_b_reg <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_B); -- BITMANIP implemented at all?
|
end if;
|
end if;
|
|
|
-- floating-point operations (Zfinx) --
|
-- floating-point operations (Zfinx) --
|
if ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+3) = "0000")) or -- FADD.S / FSUB.S
|
if ((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+3) = "0000")) or -- FADD.S / FSUB.S
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "00010")) or -- FMUL.S
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "00010")) or -- FMUL.S
|
| Line 875... |
Line 883... |
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "00100") and (execute_engine.i_reg(instr_funct3_msb_c) = '0')) or -- FSGNJ[N/X].S
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "00100") and (execute_engine.i_reg(instr_funct3_msb_c) = '0')) or -- FSGNJ[N/X].S
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "00101") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_msb_c-1) = "00")) or -- FMIN.S / FMAX.S
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "00101") and (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_msb_c-1) = "00")) or -- FMIN.S / FMAX.S
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "10100") and (execute_engine.i_reg(instr_funct3_msb_c) = '0')) or -- FEQ.S / FLT.S / FLE.S
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "10100") and (execute_engine.i_reg(instr_funct3_msb_c) = '0')) or -- FEQ.S / FLT.S / FLE.S
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "11010") and (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c+1) = "0000")) or -- FCVT.S.W*
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "11010") and (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c+1) = "0000")) or -- FCVT.S.W*
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "11000") and (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c+1) = "0000")) then -- FCVT.W*.S
|
((execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c+2) = "11000") and (execute_engine.i_reg(instr_funct12_lsb_c+4 downto instr_funct12_lsb_c+1) = "0000")) then -- FCVT.W*.S
|
decode_aux.is_float_op <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zfinx); -- FPU implemented at all?
|
decode_aux.is_f_op <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zfinx); -- FPU implemented at all?
|
end if;
|
end if;
|
|
|
-- system/environment instructions --
|
-- system/environment instructions --
|
sys_env_cmd_mask_v := funct12_ecall_c or funct12_ebreak_c or funct12_mret_c or funct12_wfi_c or funct12_dret_c; -- sum-up set bits
|
sys_env_cmd_mask_v := funct12_ecall_c or funct12_ebreak_c or funct12_mret_c or funct12_wfi_c or funct12_dret_c; -- sum-up set bits
|
decode_aux.sys_env_cmd <= execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) and sys_env_cmd_mask_v; -- set unused bits to always-zero
|
decode_aux.sys_env_cmd <= execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) and sys_env_cmd_mask_v; -- set unused bits to always-zero
|
| Line 944... |
Line 952... |
ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+0); -- unsigned ALU operation? (SLTIU, SLTU)
|
ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+0); -- unsigned ALU operation? (SLTIU, SLTU)
|
else -- branches
|
else -- branches
|
ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1); -- unsigned branches? (BLTU, BGEU)
|
ctrl_nxt(ctrl_alu_unsigned_c) <= execute_engine.i_reg(instr_funct3_lsb_c+1); -- unsigned branches? (BLTU, BGEU)
|
end if;
|
end if;
|
-- atomic store-conditional instruction (evaluate lock status) --
|
-- atomic store-conditional instruction (evaluate lock status) --
|
ctrl_nxt(ctrl_bus_ch_lock_c) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_A) and decode_aux.is_atomic_sc;
|
ctrl_nxt(ctrl_bus_ch_lock_c) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_A) and decode_aux.is_a_sc;
|
|
|
|
|
-- state machine --
|
-- state machine --
|
case execute_engine.state is
|
case execute_engine.state is
|
|
|
| Line 1034... |
Line 1042... |
ctrl_nxt(ctrl_alu_op2_c downto ctrl_alu_op0_c) <= alu_op_or_c;
|
ctrl_nxt(ctrl_alu_op2_c downto ctrl_alu_op0_c) <= alu_op_or_c;
|
when others => -- AND(I), multi-cycle / co-processor operations
|
when others => -- AND(I), multi-cycle / co-processor operations
|
ctrl_nxt(ctrl_alu_op2_c downto ctrl_alu_op0_c) <= alu_op_and_c;
|
ctrl_nxt(ctrl_alu_op2_c downto ctrl_alu_op0_c) <= alu_op_and_c;
|
end case;
|
end case;
|
|
|
-- co-processor MULDIV operation (multi-cycle)? --
|
-- co-processor MULDIV operation (multi-cycle) --
|
if ((CPU_EXTENSION_RISCV_M = true) and ((decode_aux.is_m_mul = '1') or (decode_aux.is_m_div = '1'))) or -- MUL/DIV
|
if ((CPU_EXTENSION_RISCV_M = true) and ((decode_aux.is_m_mul = '1') or (decode_aux.is_m_div = '1'))) or -- MUL/DIV
|
((CPU_EXTENSION_RISCV_Zmmul = true) and (decode_aux.is_m_mul = '1')) then -- MUL
|
((CPU_EXTENSION_RISCV_Zmmul = true) and (decode_aux.is_m_mul = '1')) then -- MUL
|
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_muldiv_c; -- use MULDIV CP
|
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_muldiv_c; -- use MULDIV CP
|
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_copro_c;
|
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_copro_c;
|
execute_engine.state_nxt <= ALU_WAIT;
|
execute_engine.state_nxt <= ALU_WAIT;
|
-- co-processor BIT-MANIPULATION operation (multi-cycle)? --
|
-- co-processor BIT-MANIPULATION operation (multi-cycle) --
|
elsif (CPU_EXTENSION_RISCV_B = true) and
|
elsif (CPU_EXTENSION_RISCV_B = true) and
|
(((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and (decode_aux.is_bitmanip_reg = '1')) or -- register operation
|
(((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alu_c(5)) and (decode_aux.is_b_reg = '1')) or -- register operation
|
((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alui_c(5)) and (decode_aux.is_bitmanip_imm = '1'))) then -- immediate operation
|
((execute_engine.i_reg(instr_opcode_lsb_c+5) = opcode_alui_c(5)) and (decode_aux.is_b_imm = '1'))) then -- immediate operation
|
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_bitmanip_c; -- use BITMANIP CP
|
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_bitmanip_c; -- use BITMANIP CP
|
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_copro_c;
|
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_copro_c;
|
execute_engine.state_nxt <= ALU_WAIT;
|
execute_engine.state_nxt <= ALU_WAIT;
|
-- co-processor SHIFT operation (multi-cycle)? --
|
-- co-processor SHIFT operation (multi-cycle) --
|
elsif (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) or
|
elsif (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c) then
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c) then
|
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_shifter_c; -- use SHIFTER CP (only relevant for shift operations)
|
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_shifter_c; -- use SHIFTER CP (only relevant for shift operations)
|
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_copro_c;
|
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_copro_c;
|
execute_engine.state_nxt <= ALU_WAIT;
|
execute_engine.state_nxt <= ALU_WAIT;
|
| Line 1106... |
Line 1114... |
else -- illegal fence instruction
|
else -- illegal fence instruction
|
execute_engine.state_nxt <= SYS_WAIT;
|
execute_engine.state_nxt <= SYS_WAIT;
|
end if;
|
end if;
|
|
|
|
|
when opcode_syscsr_c => -- system/csr access
|
|
-- ------------------------------------------------------------
|
|
if (CPU_EXTENSION_RISCV_Zicsr = true) then
|
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_env_c) then -- system/environment
|
|
execute_engine.state_nxt <= SYS_ENV;
|
|
else -- CSR access
|
|
execute_engine.state_nxt <= CSR_ACCESS;
|
|
end if;
|
|
else
|
|
execute_engine.state_nxt <= SYS_WAIT;
|
|
end if;
|
|
|
|
|
|
when opcode_fop_c => -- floating-point operations
|
when opcode_fop_c => -- floating-point operations
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
if (CPU_EXTENSION_RISCV_Zfinx = true) then
|
if (CPU_EXTENSION_RISCV_Zfinx = true) then
|
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_fpu_c; -- trigger FPU CP
|
ctrl_nxt(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) <= cp_sel_fpu_c; -- trigger FPU CP
|
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_copro_c;
|
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_copro_c;
|
| Line 1130... |
Line 1125... |
else
|
else
|
execute_engine.state_nxt <= SYS_WAIT;
|
execute_engine.state_nxt <= SYS_WAIT;
|
end if;
|
end if;
|
|
|
|
|
when others => -- illegal opcode
|
when others => -- system/csr access OR illegal opcode - nothing bad (= no commits) will happen here if there is an illegal opcode
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
|
if (CPU_EXTENSION_RISCV_Zicsr = true) then
|
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_env_c) then -- system/environment
|
|
execute_engine.state_nxt <= SYS_ENV;
|
|
else -- CSR access
|
|
execute_engine.state_nxt <= CSR_ACCESS;
|
|
end if;
|
|
else
|
execute_engine.state_nxt <= SYS_WAIT;
|
execute_engine.state_nxt <= SYS_WAIT;
|
|
end if;
|
|
|
end case;
|
end case;
|
|
|
|
|
when SYS_ENV => -- system environment operation - execution
|
when SYS_ENV => -- system environment operation - no action if illegal instruction
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
execute_engine.state_nxt <= SYS_WAIT; -- default
|
execute_engine.state_nxt <= SYS_WAIT; -- default
|
if (trap_ctrl.exc_buf(exception_iillegal_c) = '0') then -- no illegal instruction
|
if (trap_ctrl.exc_buf(exception_iillegal_c) = '0') then -- no illegal instruction
|
case decode_aux.sys_env_cmd is -- use a simplified input here (with hardwired zeros)
|
case decode_aux.sys_env_cmd is -- use a simplified input here (with hardwired zeros)
|
when funct12_ecall_c => trap_ctrl.env_call <= '1'; -- ECALL
|
when funct12_ecall_c => trap_ctrl.env_call <= '1'; -- ECALL
|
| Line 1153... |
Line 1156... |
debug_ctrl.dret <= '1';
|
debug_ctrl.dret <= '1';
|
else
|
else
|
NULL; -- executed as NOP (and raise illegal instruction exception)
|
NULL; -- executed as NOP (and raise illegal instruction exception)
|
end if;
|
end if;
|
when funct12_wfi_c => -- WFI
|
when funct12_wfi_c => -- WFI
|
if (CPU_EXTENSION_RISCV_DEBUG = true) and
|
if (CPU_EXTENSION_RISCV_DEBUG = true) and ((debug_ctrl.running = '1') or (csr.dcsr_step = '1')) then -- NOP when in debug-mode or during single-stepping
|
((debug_ctrl.running = '1') or (csr.dcsr_step = '1')) then -- act as NOP when in debug-mode or during single-stepping
|
|
NULL; -- executed as NOP
|
NULL; -- executed as NOP
|
else
|
else
|
execute_engine.sleep_nxt <= '1'; -- go to sleep mode
|
execute_engine.sleep_nxt <= '1'; -- go to sleep mode
|
end if;
|
end if;
|
when others => NULL; -- undefined / execute as NOP
|
when others => NULL; -- undefined, execute as NOP
|
end case;
|
end case;
|
end if;
|
end if;
|
|
|
|
|
when CSR_ACCESS => -- read & write status and control register (CSR)
|
when CSR_ACCESS => -- read & write status and control register (CSR) - no read/write if illegal instruction
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
-- CSR write access --
|
-- CSR write access --
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrwi_c) then -- CSRRW(I)
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrwi_c) then -- CSRRW(I)
|
csr.we_nxt <= '1'; -- always write CSR
|
csr.we_nxt <= '1'; -- always write CSR
|
| Line 1182... |
Line 1184... |
|
|
|
|
when ALU_WAIT => -- wait for multi-cycle ALU operation (co-processor) to finish
|
when ALU_WAIT => -- wait for multi-cycle ALU operation (co-processor) to finish
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_copro_c;
|
ctrl_nxt(ctrl_alu_func1_c downto ctrl_alu_func0_c) <= alu_func_copro_c;
|
if (alu_idone_i = '1') or (trap_ctrl.exc_buf(exception_iillegal_c) = '1') then -- completed or exception
|
-- wait for completion or abort on illegal instruction exception (the co-processor will also terminate operations)
|
|
if (alu_idone_i = '1') or (trap_ctrl.exc_buf(exception_iillegal_c) = '1') then
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
|
execute_engine.state_nxt <= DISPATCH;
|
execute_engine.state_nxt <= DISPATCH;
|
end if;
|
end if;
|
|
|
|
|
| Line 1208... |
Line 1211... |
end if;
|
end if;
|
|
|
|
|
when LOADSTORE_0 => -- trigger memory request
|
when LOADSTORE_0 => -- trigger memory request
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
ctrl_nxt(ctrl_bus_lock_c) <= decode_aux.is_atomic_lr; -- atomic.LR: set lock
|
ctrl_nxt(ctrl_bus_lock_c) <= decode_aux.is_a_lr; -- atomic.LR: set lock
|
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') or (decode_aux.is_atomic_lr = '1') then -- normal load or atomic load-reservate
|
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') or (decode_aux.is_a_lr = '1') then -- normal load or atomic load-reservate
|
ctrl_nxt(ctrl_bus_rd_c) <= '1'; -- read request
|
ctrl_nxt(ctrl_bus_rd_c) <= '1'; -- read request
|
else -- store
|
else -- store
|
if (decode_aux.is_atomic_sc = '0') or (CPU_EXTENSION_RISCV_A = false) then -- (normal) write request
|
if (decode_aux.is_a_sc = '0') or (CPU_EXTENSION_RISCV_A = false) then -- (normal) write request
|
ctrl_nxt(ctrl_bus_wr_c) <= '1';
|
ctrl_nxt(ctrl_bus_wr_c) <= '1';
|
else -- evaluate lock state
|
else -- evaluate lock state
|
ctrl_nxt(ctrl_bus_wr_c) <= excl_state_i; -- write request if lock is still ok
|
ctrl_nxt(ctrl_bus_wr_c) <= excl_state_i; -- write request if lock is still ok
|
end if;
|
end if;
|
end if;
|
end if;
|
| Line 1237... |
Line 1240... |
if (trap_ctrl.env_start = '1') and (trap_ctrl.cause(6 downto 5) = "00") then -- abort if SYNC EXCEPTION (from bus or illegal cmd) / no IRQs and NOT DEBUG-MODE-related
|
if (trap_ctrl.env_start = '1') and (trap_ctrl.cause(6 downto 5) = "00") then -- abort if SYNC EXCEPTION (from bus or illegal cmd) / no IRQs and NOT DEBUG-MODE-related
|
execute_engine.state_nxt <= DISPATCH;
|
execute_engine.state_nxt <= DISPATCH;
|
elsif (bus_d_wait_i = '0') then -- wait for bus to finish transaction
|
elsif (bus_d_wait_i = '0') then -- wait for bus to finish transaction
|
-- data write-back --
|
-- data write-back --
|
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') or -- normal load
|
if (execute_engine.i_reg(instr_opcode_msb_c-1) = '0') or -- normal load
|
(decode_aux.is_atomic_lr = '1') or -- atomic load-reservate
|
(decode_aux.is_a_lr = '1') or -- atomic load-reservate
|
(decode_aux.is_atomic_sc = '1') then -- atomic store-conditional
|
(decode_aux.is_a_sc = '1') then -- atomic store-conditional
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1';
|
ctrl_nxt(ctrl_rf_wb_en_c) <= '1';
|
end if;
|
end if;
|
-- remove atomic lock if this is NOT the LR.W instruction used to SET the lock --
|
-- remove atomic lock if this is NOT the LR.W instruction used to SET the lock --
|
if (decode_aux.is_atomic_lr = '0') then -- execute and evaluate atomic store-conditional
|
if (decode_aux.is_a_lr = '0') then -- execute and evaluate atomic store-conditional
|
ctrl_nxt(ctrl_bus_de_lock_c) <= '1';
|
ctrl_nxt(ctrl_bus_de_lock_c) <= '1';
|
end if;
|
end if;
|
execute_engine.state_nxt <= DISPATCH;
|
execute_engine.state_nxt <= DISPATCH;
|
end if;
|
end if;
|
|
|
| Line 1258... |
Line 1261... |
end case;
|
end case;
|
end process execute_engine_fsm_comb;
|
end process execute_engine_fsm_comb;
|
|
|
|
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
-- Invalid Instruction / CSR access check
|
-- Illegal Instruction and CSR Access Check
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
|
|
-- CSR Access Check -----------------------------------------------------------------------
|
-- CSR Access Check -----------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
csr_access_check: process(execute_engine.i_reg, decode_aux, csr, debug_ctrl)
|
csr_access_check: process(execute_engine.i_reg, decode_aux, csr, debug_ctrl)
|
| Line 1384... |
Line 1387... |
|
|
when opcode_lui_c | opcode_auipc_c | opcode_jal_c => -- check sufficient LUI, UIPC, JAL (only check actual OPCODE)
|
when opcode_lui_c | opcode_auipc_c | opcode_jal_c => -- check sufficient LUI, UIPC, JAL (only check actual OPCODE)
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
-- illegal E-CPU register? --
|
-- illegal E-CPU register? --
|
illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and execute_engine.i_reg(instr_rd_msb_c);
|
illegal_register <= execute_engine.i_reg(instr_rd_msb_c);
|
|
|
when opcode_alu_c => -- check ALU.funct3 & ALU.funct7
|
when opcode_alu_c => -- check ALU.funct3 & ALU.funct7
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
if (((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_subadd_c) or (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c)) and
|
if (((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_subadd_c) or (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c)) and
|
(execute_engine.i_reg(instr_funct7_msb_c-2 downto instr_funct7_lsb_c) = "00000") and (execute_engine.i_reg(instr_funct7_msb_c) = '0')) or
|
(execute_engine.i_reg(instr_funct7_msb_c-2 downto instr_funct7_lsb_c) = "00000") and (execute_engine.i_reg(instr_funct7_msb_c) = '0')) or
|
| Line 1402... |
Line 1405... |
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
elsif ((CPU_EXTENSION_RISCV_M = true) or (CPU_EXTENSION_RISCV_Zmmul = false)) and (decode_aux.is_m_mul = '1') then -- valid MUL instruction?
|
elsif ((CPU_EXTENSION_RISCV_M = true) or (CPU_EXTENSION_RISCV_Zmmul = false)) and (decode_aux.is_m_mul = '1') then -- valid MUL instruction?
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
elsif (CPU_EXTENSION_RISCV_M = true) and (decode_aux.is_m_div = '1') then -- valid DIV instruction?
|
elsif (CPU_EXTENSION_RISCV_M = true) and (decode_aux.is_m_div = '1') then -- valid DIV instruction?
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
elsif (CPU_EXTENSION_RISCV_B = true) and (decode_aux.is_bitmanip_reg = '1') then -- valid BITMANIP instruction?
|
elsif (CPU_EXTENSION_RISCV_B = true) and (decode_aux.is_b_reg = '1') then -- valid BITMANIP instruction?
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
else
|
else
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
end if;
|
end if;
|
-- illegal E-CPU register? --
|
-- illegal E-CPU register? --
|
illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rd_msb_c) or execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rs2_msb_c));
|
illegal_register <= execute_engine.i_reg(instr_rd_msb_c) or execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rs2_msb_c);
|
|
|
when opcode_alui_c => -- check ALUI.funct7
|
when opcode_alui_c => -- check ALUI.funct7
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_subadd_c) or
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_subadd_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_slt_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_slt_c) or
|
| Line 1423... |
Line 1426... |
((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) and -- shift logical left
|
((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sll_c) and -- shift logical left
|
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000000")) or
|
(execute_engine.i_reg(instr_funct7_msb_c downto instr_funct7_lsb_c) = "0000000")) or
|
((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c) and -- shift right
|
((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sr_c) and -- shift right
|
((execute_engine.i_reg(instr_funct7_msb_c-2 downto instr_funct7_lsb_c) = "00000") and (execute_engine.i_reg(instr_funct7_msb_c) = '0'))) then -- valid base ALUI instruction?
|
((execute_engine.i_reg(instr_funct7_msb_c-2 downto instr_funct7_lsb_c) = "00000") and (execute_engine.i_reg(instr_funct7_msb_c) = '0'))) then -- valid base ALUI instruction?
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
elsif (CPU_EXTENSION_RISCV_B = true) and (decode_aux.is_bitmanip_imm = '1') then -- valid BITMANIP immediate instruction?
|
elsif (CPU_EXTENSION_RISCV_B = true) and (decode_aux.is_b_imm = '1') then -- valid BITMANIP immediate instruction?
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
else
|
else
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
end if;
|
end if;
|
-- illegal E-CPU register? --
|
-- illegal E-CPU register? --
|
illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c));
|
illegal_register <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c);
|
|
|
when opcode_load_c => -- check LOAD.funct3
|
when opcode_load_c => -- check LOAD.funct3
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lb_c) or
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lb_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lh_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_lh_c) or
|
| Line 1443... |
Line 1446... |
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
else
|
else
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
end if;
|
end if;
|
-- illegal E-CPU register? --
|
-- illegal E-CPU register? --
|
illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c));
|
illegal_register <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c);
|
|
|
when opcode_store_c => -- check STORE.funct3
|
when opcode_store_c => -- check STORE.funct3
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sb_c) or
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sb_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sh_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_sh_c) or
|
| Line 1455... |
Line 1458... |
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
else
|
else
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
end if;
|
end if;
|
-- illegal E-CPU register? --
|
-- illegal E-CPU register? --
|
illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs2_msb_c) or execute_engine.i_reg(instr_rs1_msb_c));
|
illegal_register <= execute_engine.i_reg(instr_rs2_msb_c) or execute_engine.i_reg(instr_rs1_msb_c);
|
|
|
when opcode_atomic_c => -- atomic instructions
|
when opcode_atomic_c => -- atomic instructions
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
if (CPU_EXTENSION_RISCV_A = true) then
|
if (CPU_EXTENSION_RISCV_A = true) then
|
if (execute_engine.i_reg(instr_funct5_msb_c downto instr_funct5_lsb_c) = "00010") then -- LR
|
if (execute_engine.i_reg(instr_funct5_msb_c downto instr_funct5_lsb_c) = "00010") then -- LR
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
-- illegal E-CPU register? --
|
-- illegal E-CPU register? --
|
illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c));
|
illegal_register <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c);
|
elsif (execute_engine.i_reg(instr_funct5_msb_c downto instr_funct5_lsb_c) = "00011") then -- SC
|
elsif (execute_engine.i_reg(instr_funct5_msb_c downto instr_funct5_lsb_c) = "00011") then -- SC
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
-- illegal E-CPU register? --
|
-- illegal E-CPU register? --
|
illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rs2_msb_c) or execute_engine.i_reg(instr_rd_msb_c));
|
illegal_register <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rs2_msb_c) or execute_engine.i_reg(instr_rd_msb_c);
|
else
|
else
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
end if;
|
end if;
|
else
|
else
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
| Line 1488... |
Line 1491... |
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
else
|
else
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
end if;
|
end if;
|
-- illegal E-CPU register? --
|
-- illegal E-CPU register? --
|
illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs2_msb_c) or execute_engine.i_reg(instr_rs1_msb_c));
|
illegal_register <= execute_engine.i_reg(instr_rs2_msb_c) or execute_engine.i_reg(instr_rs1_msb_c);
|
|
|
when opcode_jalr_c => -- check JALR.funct3
|
when opcode_jalr_c => -- check JALR.funct3
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "000") then
|
if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "000") then
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
else
|
else
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
end if;
|
end if;
|
-- illegal E-CPU register? --
|
-- illegal E-CPU register? --
|
illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c));
|
illegal_register <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c);
|
|
|
when opcode_fence_c => -- check FENCE.funct3
|
when opcode_fence_c => -- check FENCE.funct3
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
if ((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fencei_c) and (CPU_EXTENSION_RISCV_Zifencei = true)) or -- FENCE.I
|
if ((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fencei_c) and (CPU_EXTENSION_RISCV_Zifencei = true)) or -- FENCE.I
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fence_c) then -- FENCE
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fence_c) then -- FENCE
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
else
|
else
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
end if;
|
end if;
|
-- illegal E-CPU register? --
|
-- NOTE: ignore all remaining bit fields here
|
illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c));
|
|
|
|
when opcode_syscsr_c => -- check system instructions
|
when opcode_syscsr_c => -- check system instructions
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
-- CSR access --
|
-- CSR access --
|
if ((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or
|
if ((execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or
|
| Line 1523... |
Line 1525... |
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrsi_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrsi_c) or
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrci_c)) and
|
(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrci_c)) and
|
(csr_acc_valid = '1') then -- valid CSR access?
|
(csr_acc_valid = '1') then -- valid CSR access?
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
-- illegal E-CPU register? --
|
-- illegal E-CPU register? --
|
if (CPU_EXTENSION_RISCV_E = true) then
|
|
if (execute_engine.i_reg(instr_funct3_msb_c) = '0') then -- reg-reg CSR
|
if (execute_engine.i_reg(instr_funct3_msb_c) = '0') then -- reg-reg CSR
|
illegal_register <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c);
|
illegal_register <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c);
|
else -- reg-imm CSR
|
else -- reg-imm CSR
|
illegal_register <= execute_engine.i_reg(instr_rd_msb_c);
|
illegal_register <= execute_engine.i_reg(instr_rd_msb_c);
|
end if;
|
end if;
|
end if;
|
-- system: ecall, ebreak, mret, wfi, dret --
|
-- ecall, ebreak, mret, wfi, dret --
|
|
elsif (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "000") and
|
elsif (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = "000") and
|
(decode_aux.rs1_zero = '1') and (decode_aux.rd_zero = '1') and
|
(decode_aux.rs1_zero = '1') and (decode_aux.rd_zero = '1') and
|
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_ecall_c) or -- ECALL
|
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_ecall_c) or -- ECALL
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_ebreak_c) or -- EBREAK
|
(execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_ebreak_c) or -- EBREAK
|
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_mret_c) and (csr.priv_m_mode = '1')) or -- MRET (only allowed in M-mode)
|
((execute_engine.i_reg(instr_funct12_msb_c downto instr_funct12_lsb_c) = funct12_mret_c) and (csr.priv_m_mode = '1')) or -- MRET (only allowed in M-mode)
|
| Line 1547... |
Line 1547... |
|
|
when opcode_fop_c => -- floating point operations - single/dual operands
|
when opcode_fop_c => -- floating point operations - single/dual operands
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
if (CPU_EXTENSION_RISCV_Zfinx = true) and -- F extension implemented
|
if (CPU_EXTENSION_RISCV_Zfinx = true) and -- F extension implemented
|
(execute_engine.i_reg(instr_funct7_lsb_c+1 downto instr_funct7_lsb_c) = float_single_c) and -- single-precision operations only
|
(execute_engine.i_reg(instr_funct7_lsb_c+1 downto instr_funct7_lsb_c) = float_single_c) and -- single-precision operations only
|
(decode_aux.is_float_op = '1') then -- is correct/supported floating-point instruction
|
(decode_aux.is_f_op = '1') then -- is correct/supported floating-point instruction
|
illegal_instruction <= '0';
|
illegal_instruction <= '0';
|
else
|
else
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
end if;
|
end if;
|
-- illegal E-CPU register? --
|
-- illegal E-CPU register? --
|
-- FIXME: rs2 is not checked!
|
-- FIXME: rs2 is not checked!
|
illegal_register <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and (execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c));
|
illegal_register <= execute_engine.i_reg(instr_rs1_msb_c) or execute_engine.i_reg(instr_rd_msb_c);
|
|
|
when others => -- undefined instruction -> illegal!
|
when others => -- undefined instruction -> illegal!
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
illegal_instruction <= '1';
|
illegal_instruction <= '1';
|
|
|
| Line 1570... |
Line 1570... |
illegal_register <= '0';
|
illegal_register <= '0';
|
end if;
|
end if;
|
end process illegal_instruction_check;
|
end process illegal_instruction_check;
|
|
|
-- any illegal condition? --
|
-- any illegal condition? --
|
trap_ctrl.instr_il <= illegal_instruction or illegal_opcode_lsbs or illegal_register or illegal_compressed;
|
trap_ctrl.instr_il <= illegal_opcode_lsbs or -- illegal opcode MSB bits
|
|
illegal_instruction or -- illegal instruction format/layout
|
|
(bool_to_ulogic_f(CPU_EXTENSION_RISCV_E) and illegal_register) or -- illegal register access in E extension
|
|
illegal_compressed; -- illegal compressed instruction
|
|
|
|
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
-- Exception and Interrupt (= Trap) Control
|
-- Exception and Interrupt (= Traps) Control
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
|
|
-- Trap Controller ------------------------------------------------------------------------
|
-- Trap Controller ------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
trap_controller: process(rstn_i, clk_i)
|
trap_controller: process(rstn_i, clk_i)
|
variable mode_m_v, mode_u_v : std_ulogic;
|
variable mode_m_v, mode_u_v : std_ulogic;
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
trap_ctrl.exc_buf <= (others => '0');
|
trap_ctrl.exc_buf <= (others => '0');
|
trap_ctrl.irq_buf <= (others => '0');
|
trap_ctrl.irq_buf <= (others => '0');
|
trap_ctrl.exc_ack <= '0';
|
trap_ctrl.exc_clr <= '0';
|
trap_ctrl.env_start <= '0';
|
trap_ctrl.env_start <= '0';
|
trap_ctrl.cause <= (others => '0');
|
trap_ctrl.cause <= (others => '0');
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
if (CPU_EXTENSION_RISCV_Zicsr = true) then
|
if (CPU_EXTENSION_RISCV_Zicsr = true) then
|
|
|
-- exception queue: misaligned load/store/instruction address --
|
-- exception queue: misaligned load/store/instruction address --
|
trap_ctrl.exc_buf(exception_lalign_c) <= (trap_ctrl.exc_buf(exception_lalign_c) or ma_load_i) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_lalign_c) <= (trap_ctrl.exc_buf(exception_lalign_c) or ma_load_i) and (not trap_ctrl.exc_clr);
|
trap_ctrl.exc_buf(exception_salign_c) <= (trap_ctrl.exc_buf(exception_salign_c) or ma_store_i) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_salign_c) <= (trap_ctrl.exc_buf(exception_salign_c) or ma_store_i) and (not trap_ctrl.exc_clr);
|
trap_ctrl.exc_buf(exception_ialign_c) <= (trap_ctrl.exc_buf(exception_ialign_c) or trap_ctrl.instr_ma) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_ialign_c) <= (trap_ctrl.exc_buf(exception_ialign_c) or trap_ctrl.instr_ma) and (not trap_ctrl.exc_clr);
|
|
|
-- exception queue: load/store/instruction bus access error --
|
-- exception queue: load/store/instruction bus access error --
|
trap_ctrl.exc_buf(exception_laccess_c) <= (trap_ctrl.exc_buf(exception_laccess_c) or be_load_i) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_laccess_c) <= (trap_ctrl.exc_buf(exception_laccess_c) or be_load_i) and (not trap_ctrl.exc_clr);
|
trap_ctrl.exc_buf(exception_saccess_c) <= (trap_ctrl.exc_buf(exception_saccess_c) or be_store_i) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_saccess_c) <= (trap_ctrl.exc_buf(exception_saccess_c) or be_store_i) and (not trap_ctrl.exc_clr);
|
trap_ctrl.exc_buf(exception_iaccess_c) <= (trap_ctrl.exc_buf(exception_iaccess_c) or trap_ctrl.instr_be) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_iaccess_c) <= (trap_ctrl.exc_buf(exception_iaccess_c) or trap_ctrl.instr_be) and (not trap_ctrl.exc_clr);
|
|
|
-- exception queue: illegal instruction / environment calls --
|
-- exception queue: illegal instruction / environment calls --
|
trap_ctrl.exc_buf(exception_m_envcall_c) <= (trap_ctrl.exc_buf(exception_m_envcall_c) or (trap_ctrl.env_call and csr.priv_m_mode)) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_m_envcall_c) <= (trap_ctrl.exc_buf(exception_m_envcall_c) or (trap_ctrl.env_call and csr.priv_m_mode)) and (not trap_ctrl.exc_clr);
|
trap_ctrl.exc_buf(exception_u_envcall_c) <= (trap_ctrl.exc_buf(exception_u_envcall_c) or (trap_ctrl.env_call and csr.priv_u_mode)) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_u_envcall_c) <= (trap_ctrl.exc_buf(exception_u_envcall_c) or (trap_ctrl.env_call and csr.priv_u_mode)) and (not trap_ctrl.exc_clr);
|
trap_ctrl.exc_buf(exception_iillegal_c) <= (trap_ctrl.exc_buf(exception_iillegal_c) or trap_ctrl.instr_il) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_iillegal_c) <= (trap_ctrl.exc_buf(exception_iillegal_c) or trap_ctrl.instr_il) and (not trap_ctrl.exc_clr);
|
|
|
-- exception queue: break point --
|
-- exception queue: break point --
|
if (CPU_EXTENSION_RISCV_DEBUG = true) then
|
if (CPU_EXTENSION_RISCV_DEBUG = true) then
|
trap_ctrl.exc_buf(exception_break_c) <= (not trap_ctrl.exc_ack) and (trap_ctrl.exc_buf(exception_break_c) or
|
trap_ctrl.exc_buf(exception_break_c) <= (not trap_ctrl.exc_clr) and (trap_ctrl.exc_buf(exception_break_c) or
|
((trap_ctrl.break_point and csr.priv_m_mode and (not csr.dcsr_ebreakm) and (not debug_ctrl.running)) or -- enable break to machine-trap-handler when in machine mode on "ebreak"
|
(trap_ctrl.break_point and csr.priv_m_mode and (not csr.dcsr_ebreakm) and (not debug_ctrl.running)) or -- break to machine-trap-handler when in machine mode on "ebreak"
|
(trap_ctrl.break_point and csr.priv_u_mode and (not csr.dcsr_ebreaku) and (not debug_ctrl.running)))); -- enable break to machine-trap-handler when in user mode on "ebreak"
|
(trap_ctrl.break_point and csr.priv_u_mode and (not csr.dcsr_ebreaku) and (not debug_ctrl.running))); -- break to machine-trap-handler when in user mode on "ebreak"
|
else
|
else
|
trap_ctrl.exc_buf(exception_break_c) <= (trap_ctrl.exc_buf(exception_break_c) or trap_ctrl.break_point) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_break_c) <= (trap_ctrl.exc_buf(exception_break_c) or trap_ctrl.break_point) and (not trap_ctrl.exc_clr);
|
end if;
|
end if;
|
|
|
-- exception buffer: enter debug mode --
|
-- exception/interrupt buffer: enter debug mode --
|
trap_ctrl.exc_buf(exception_db_break_c) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG) and (trap_ctrl.exc_buf(exception_db_break_c) or debug_ctrl.trig_break) and (not trap_ctrl.exc_ack);
|
trap_ctrl.exc_buf(exception_db_break_c) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG) and (trap_ctrl.exc_buf(exception_db_break_c) or debug_ctrl.trig_break) and (not trap_ctrl.exc_clr);
|
trap_ctrl.irq_buf(interrupt_db_halt_c) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG) and debug_ctrl.trig_halt;
|
trap_ctrl.irq_buf(interrupt_db_halt_c) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG) and debug_ctrl.trig_halt;
|
trap_ctrl.irq_buf(interrupt_db_step_c) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG) and debug_ctrl.trig_step;
|
trap_ctrl.irq_buf(interrupt_db_step_c) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_DEBUG) and debug_ctrl.trig_step;
|
|
|
-- interrupt buffer: machine software/external/timer interrupt --
|
-- interrupt buffer: machine software/external/timer interrupt --
|
trap_ctrl.irq_buf(interrupt_msw_irq_c) <= csr.mie_msie and msw_irq_i;
|
trap_ctrl.irq_buf(interrupt_msw_irq_c) <= csr.mie_msie and msw_irq_i;
|
| Line 1633... |
Line 1636... |
-- trap environment control --
|
-- trap environment control --
|
if (trap_ctrl.env_start = '0') then -- no started trap handler
|
if (trap_ctrl.env_start = '0') then -- no started trap handler
|
if (trap_ctrl.exc_fire = '1') or ((trap_ctrl.irq_fire = '1') and -- exception triggered!
|
if (trap_ctrl.exc_fire = '1') or ((trap_ctrl.irq_fire = '1') and -- exception triggered!
|
((execute_engine.state = EXECUTE) or (execute_engine.state = TRAP_ENTER))) then -- fire IRQs in EXECUTE or TRAP state only to continue execution even on permanent IRQ
|
((execute_engine.state = EXECUTE) or (execute_engine.state = TRAP_ENTER))) then -- fire IRQs in EXECUTE or TRAP state only to continue execution even on permanent IRQ
|
trap_ctrl.cause <= trap_ctrl.cause_nxt; -- capture source ID for program (for mcause csr)
|
trap_ctrl.cause <= trap_ctrl.cause_nxt; -- capture source ID for program (for mcause csr)
|
trap_ctrl.exc_ack <= '1'; -- clear exceptions (no ack mask: these have highest priority and are always evaluated first!)
|
trap_ctrl.exc_clr <= '1'; -- clear exceptions (no ack mask: these have highest priority and are always evaluated first!)
|
trap_ctrl.env_start <= '1'; -- now execute engine can start trap handler
|
trap_ctrl.env_start <= '1'; -- now execute engine can start trap handler
|
end if;
|
end if;
|
else -- trap waiting to get started
|
else -- trap waiting to get started
|
if (trap_ctrl.env_start_ack = '1') then -- start of trap handler acknowledged by execution engine
|
if (trap_ctrl.env_start_ack = '1') then -- start of trap handler acknowledged by execution engine
|
trap_ctrl.exc_ack <= '0';
|
trap_ctrl.exc_clr <= '0';
|
trap_ctrl.env_start <= '0';
|
trap_ctrl.env_start <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
| Line 1659... |
Line 1662... |
|
|
-- Trap Priority Encoder ------------------------------------------------------------------
|
-- Trap Priority Encoder ------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
trap_priority: process(trap_ctrl)
|
trap_priority: process(trap_ctrl)
|
begin
|
begin
|
-- defaults --
|
|
trap_ctrl.cause_nxt <= (others => '0');
|
|
|
|
-- NOTE: Synchronous exceptions (from trap_ctrl.exc_buf) have higher priority than asynchronous
|
|
-- exceptions (from trap_ctrl.irq_buf).
|
|
|
|
-- ----------------------------------------------------------------------------------------
|
-- ----------------------------------------------------------------------------------------
|
-- the following traps are caused by *synchronous* exceptions; we do not need a
|
-- the following traps are caused by *synchronous* exceptions; we do not need a
|
-- specific acknowledge mask since only _one_ exception (the one with highest priority)
|
-- specific acknowledge mask since only _one_ exception (the one with highest priority)
|
-- is allowed to kick in at once
|
-- is allowed to kick in at once
|
-- ----------------------------------------------------------------------------------------
|
-- ----------------------------------------------------------------------------------------
|
| Line 1713... |
Line 1710... |
|
|
-- exception: 0.5 load access fault --
|
-- exception: 0.5 load access fault --
|
elsif (trap_ctrl.exc_buf(exception_laccess_c) = '1') then
|
elsif (trap_ctrl.exc_buf(exception_laccess_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_lbe_c;
|
trap_ctrl.cause_nxt <= trap_lbe_c;
|
|
|
|
|
-- ----------------------------------------------------------------------------------------
|
-- ----------------------------------------------------------------------------------------
|
-- (re-)enter debug mode requests: basically, these are standard traps that have some
|
-- (re-)enter debug mode requests: basically, these are standard traps that have some
|
-- special handling - they have the highest INTERRUPT priority in order to go to debug when requested
|
-- special handling - they have the highest INTERRUPT priority in order to go to debug when requested
|
-- even if other IRQs are pending right now
|
-- even if other IRQs are pending right now
|
-- ----------------------------------------------------------------------------------------
|
-- ----------------------------------------------------------------------------------------
|
|
|
-- break instruction --
|
-- break instruction (sync) --
|
elsif (CPU_EXTENSION_RISCV_DEBUG = true) and (trap_ctrl.exc_buf(exception_db_break_c) = '1') then
|
elsif (trap_ctrl.exc_buf(exception_db_break_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_db_break_c;
|
trap_ctrl.cause_nxt <= trap_db_break_c;
|
|
|
-- external halt request --
|
-- external halt request (async) --
|
elsif (CPU_EXTENSION_RISCV_DEBUG = true) and (trap_ctrl.irq_buf(interrupt_db_halt_c) = '1') then
|
elsif (trap_ctrl.irq_buf(interrupt_db_halt_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_db_halt_c;
|
trap_ctrl.cause_nxt <= trap_db_halt_c;
|
|
|
-- single stepping --
|
-- single stepping (async) --
|
elsif (CPU_EXTENSION_RISCV_DEBUG = true) and (trap_ctrl.irq_buf(interrupt_db_step_c) = '1') then
|
elsif (trap_ctrl.irq_buf(interrupt_db_step_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_db_step_c;
|
trap_ctrl.cause_nxt <= trap_db_step_c;
|
|
|
|
|
-- ----------------------------------------------------------------------------------------
|
-- ----------------------------------------------------------------------------------------
|
-- the following traps are caused by *asynchronous* exceptions (= interrupts)
|
-- custom FAST interrupts (*asynchronous* exceptions)
|
-- ----------------------------------------------------------------------------------------
|
-- ----------------------------------------------------------------------------------------
|
|
|
-- custom FAST interrupt requests --
|
|
|
|
-- interrupt: 1.16 fast interrupt channel 0 --
|
-- interrupt: 1.16 fast interrupt channel 0 --
|
elsif (trap_ctrl.irq_buf(interrupt_firq_0_c) = '1') then
|
elsif (trap_ctrl.irq_buf(interrupt_firq_0_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_firq0_c;
|
trap_ctrl.cause_nxt <= trap_firq0_c;
|
|
|
-- interrupt: 1.17 fast interrupt channel 1 --
|
-- interrupt: 1.17 fast interrupt channel 1 --
|
| Line 1803... |
Line 1796... |
|
|
-- interrupt: 1.31 fast interrupt channel 15 --
|
-- interrupt: 1.31 fast interrupt channel 15 --
|
elsif (trap_ctrl.irq_buf(interrupt_firq_15_c) = '1') then
|
elsif (trap_ctrl.irq_buf(interrupt_firq_15_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_firq15_c;
|
trap_ctrl.cause_nxt <= trap_firq15_c;
|
|
|
|
-- ----------------------------------------------------------------------------------------
|
-- standard RISC-V interrupts --
|
-- standard RISC-V interrupts (*asynchronous* exceptions)
|
|
-- ----------------------------------------------------------------------------------------
|
|
|
-- interrupt: 1.11 machine external interrupt --
|
-- interrupt: 1.11 machine external interrupt --
|
elsif (trap_ctrl.irq_buf(interrupt_mext_irq_c) = '1') then
|
elsif (trap_ctrl.irq_buf(interrupt_mext_irq_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_mei_c;
|
trap_ctrl.cause_nxt <= trap_mei_c;
|
|
|
-- interrupt: 1.3 machine SW interrupt --
|
-- interrupt: 1.3 machine SW interrupt --
|
elsif (trap_ctrl.irq_buf(interrupt_msw_irq_c) = '1') then
|
elsif (trap_ctrl.irq_buf(interrupt_msw_irq_c) = '1') then
|
trap_ctrl.cause_nxt <= trap_msi_c;
|
trap_ctrl.cause_nxt <= trap_msi_c;
|
|
|
-- interrupt: 1.7 machine timer interrupt --
|
-- interrupt: 1.7 machine timer interrupt --
|
elsif (trap_ctrl.irq_buf(interrupt_mtime_irq_c) = '1') then
|
else--if (trap_ctrl.irq_buf(interrupt_mtime_irq_c) = '1') then -- last condition, so NO IF required
|
trap_ctrl.cause_nxt <= trap_mti_c;
|
trap_ctrl.cause_nxt <= trap_mti_c;
|
|
|
end if;
|
end if;
|
end process trap_priority;
|
end process trap_priority;
|
|
|
|
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
-- Control and Status Registers (CSRs)
|
-- Control and Status Registers (CSRs)
|
-- ****************************************************************************************************************************
|
-- ****************************************************************************************************************************
|
|
|
-- Control and Status Registers Write Data ------------------------------------------------
|
-- Control and Status Registers - Write Data ----------------------------------------------
|
-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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csr_write_data: process(execute_engine.i_reg, csr.rdata, rs1_i)
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csr_write_data: process(execute_engine.i_reg, csr.rdata, rs1_i)
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variable csr_operand_v : std_ulogic_vector(data_width_c-1 downto 0);
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variable csr_imm_v : std_ulogic_vector(data_width_c-1 downto 0);
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begin
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begin
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-- CSR operand source --
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-- tiny ALU to compute CSR write data --
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if (execute_engine.i_reg(instr_funct3_msb_c) = '1') then -- immediate
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csr_imm_v := (others => '0');
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csr_operand_v := (others => '0');
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csr_imm_v(4 downto 0) := execute_engine.i_reg(19 downto 15); -- uimm5
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csr_operand_v(4 downto 0) := execute_engine.i_reg(19 downto 15); -- uimm5
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case execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) is
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else -- register
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when funct3_csrrw_c => csr.wdata <= rs1_i;
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csr_operand_v := rs1_i;
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when funct3_csrrs_c => csr.wdata <= csr.rdata or rs1_i;
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end if;
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when funct3_csrrc_c => csr.wdata <= csr.rdata and (not rs1_i);
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-- tiny ALU for CSR write operations --
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when funct3_csrrwi_c => csr.wdata <= csr_imm_v;
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case execute_engine.i_reg(instr_funct3_lsb_c+1 downto instr_funct3_lsb_c) is
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when funct3_csrrsi_c => csr.wdata <= csr.rdata or csr_imm_v;
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when "10" => csr.wdata <= csr.rdata or csr_operand_v; -- CSRRS(I)
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when funct3_csrrci_c => csr.wdata <= csr.rdata and (not csr_imm_v);
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when "11" => csr.wdata <= csr.rdata and (not csr_operand_v); -- CSRRC(I)
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when others => csr.wdata <= (others => '-'); -- undefined
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when others => csr.wdata <= csr_operand_v; -- CSRRW(I)
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end case;
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end case;
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end process csr_write_data;
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end process csr_write_data;
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-- Control and Status Registers - Write Access --------------------------------------------
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-- Control and Status Registers - Write Access --------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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csr_write_access: process(rstn_i, clk_i)
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csr_write_access: process(rstn_i, clk_i)
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variable cause_v : std_ulogic_vector(6 downto 0);
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variable cause_v : std_ulogic_vector(6 downto 0);
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begin
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begin
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-- NOTE: If <dedicated_reset_c> = true then <def_rst_val_c> evaluates to '-'. Register that reset to <def_rst_val_c> do
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-- NOTE: If <dedicated_reset_c> = true then <def_rst_val_c> evaluates to '-'. Registers that reset to <def_rst_val_c>
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-- NOT actually have a real reset by default (def_rst_val_c = '-') and have to be explicitly initialized by software!
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-- do NOT actually have a real reset by default and have to be explicitly initialized by software!
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-- see: https://forums.xilinx.com/t5/General-Technical-Discussion/quot-Don-t-care-quot-reset-value/td-p/412845
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-- see: https://forums.xilinx.com/t5/General-Technical-Discussion/quot-Don-t-care-quot-reset-value/td-p/412845
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if (rstn_i = '0') then
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if (rstn_i = '0') then
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csr.we <= '0';
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csr.we <= '0';
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--
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--
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csr.mstatus_mie <= '0';
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csr.mstatus_mie <= '0';
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| Line 2078... |
Line 2071... |
-- --------------------------------------------------------------------
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-- --------------------------------------------------------------------
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if (CPU_EXTENSION_RISCV_Zfinx = true) and (trap_ctrl.exc_buf(exception_iillegal_c) = '0') then -- no illegal instruction
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if (CPU_EXTENSION_RISCV_Zfinx = true) and (trap_ctrl.exc_buf(exception_iillegal_c) = '0') then -- no illegal instruction
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csr.fflags <= csr.fflags or fpu_flags_i; -- accumulate flags ("accrued exception flags")
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csr.fflags <= csr.fflags or fpu_flags_i; -- accumulate flags ("accrued exception flags")
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end if;
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end if;
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-- mcause, mepc, mtval: write machine trap cause, PC and trap value register --
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-- TRAP ENTER: write machine trap cause, PC and trap value register --
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-- --------------------------------------------------------------------
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-- --------------------------------------------------------------------
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if (trap_ctrl.env_start_ack = '1') then -- trap handler starting?
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if (trap_ctrl.env_start_ack = '1') then -- trap handler starting?
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|
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if (CPU_EXTENSION_RISCV_DEBUG = false) or ((trap_ctrl.cause(5) = '0') and -- update mtval/mepc/mcause only when NOT ENTRY debug mode exception
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if (CPU_EXTENSION_RISCV_DEBUG = false) or ((trap_ctrl.cause(5) = '0') and -- update mtval/mepc/mcause only when NOT ENTRY debug mode exception
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(debug_ctrl.running = '0')) then -- and NOT IN debug mode
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(debug_ctrl.running = '0')) then -- and NOT IN debug mode
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| Line 2429... |
Line 2422... |
-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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csr_read_access: process(rstn_i, clk_i)
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csr_read_access: process(rstn_i, clk_i)
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variable csr_addr_v : std_ulogic_vector(11 downto 0);
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variable csr_addr_v : std_ulogic_vector(11 downto 0);
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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csr.rdata <= (others => '0'); -- default output
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csr.rdata <= (others => '0'); -- default output, unimplemented CSRs are hardwired to zero
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if (CPU_EXTENSION_RISCV_Zicsr = true) then
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if (CPU_EXTENSION_RISCV_Zicsr = true) then
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csr_addr_v(11 downto 10) := csr.addr(11 downto 10);
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csr_addr_v(11 downto 10) := csr.addr(11 downto 10);
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csr_addr_v(09 downto 08) := (others => csr.addr(8)); -- !!! WARNING: MACHINE (11) and USER (00) registers ONLY !!!
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csr_addr_v(09 downto 08) := (others => csr.addr(8)); -- !!! WARNING: MACHINE (11) and USER (00) registers ONLY !!!
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csr_addr_v(07 downto 00) := csr.addr(07 downto 00);
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csr_addr_v(07 downto 00) := csr.addr(07 downto 00);
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case csr_addr_v is
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case csr_addr_v is
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| Line 2735... |
Line 2728... |
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-- CSR read data output --
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-- CSR read data output --
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csr_rdata_o <= csr.rdata;
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csr_rdata_o <= csr.rdata;
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|
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|
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-- ****************************************************************************************************************************
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-- CPU Debug Mode (Part of the On-Chip Debugger)
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-- ****************************************************************************************************************************
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|
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-- Debug Control --------------------------------------------------------------------------
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-- Debug Control --------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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debug_control: process(rstn_i, clk_i)
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debug_control: process(rstn_i, clk_i)
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begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
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| Line 2798... |
Line 2795... |
debug_ctrl.trig_step <= csr.dcsr_step and (not debug_ctrl.running); -- single-step mode (trigger when NOT CURRENTLY in debug mode)
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debug_ctrl.trig_step <= csr.dcsr_step and (not debug_ctrl.running); -- single-step mode (trigger when NOT CURRENTLY in debug mode)
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|
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-- Debug Control and Status Register (dcsr) - Read-Back -----------------------------------
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-- Debug Control and Status Register (dcsr) - Read-Back -----------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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dcsr_readback_false:
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|
if (CPU_EXTENSION_RISCV_DEBUG = false) generate
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|
csr.dcsr_rd <= (others => '-');
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|
end generate;
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|
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dcsr_readback_true:
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|
if (CPU_EXTENSION_RISCV_DEBUG = true) generate
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csr.dcsr_rd(31 downto 28) <= "0100"; -- xdebugver: external debug support compatible to spec
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csr.dcsr_rd(31 downto 28) <= "0100"; -- xdebugver: external debug support compatible to spec
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csr.dcsr_rd(27 downto 16) <= (others => '0'); -- reserved
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csr.dcsr_rd(27 downto 16) <= (others => '0'); -- reserved
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csr.dcsr_rd(15) <= csr.dcsr_ebreakm; -- ebreakm: what happens on ebreak in m-mode? (normal trap OR debug-enter)
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csr.dcsr_rd(15) <= csr.dcsr_ebreakm; -- ebreakm: what happens on ebreak in m-mode? (normal trap OR debug-enter)
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csr.dcsr_rd(14) <= '0'; -- ebreakh: hypervisor mode not implemented
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csr.dcsr_rd(14) <= '0'; -- ebreakh: hypervisor mode not implemented
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csr.dcsr_rd(13) <= '0'; -- ebreaks: supervisor mode not implemented
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csr.dcsr_rd(13) <= '0'; -- ebreaks: supervisor mode not implemented
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csr.dcsr_rd(12) <= csr.dcsr_ebreaku when (CPU_EXTENSION_RISCV_U = true) else '0'; -- ebreaku: what happens on ebreak in u-mode? (normal trap OR debug-enter)
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csr.dcsr_rd(12) <= csr.dcsr_ebreaku when (CPU_EXTENSION_RISCV_U = true) else '0'; -- ebreaku: what happens on ebreak in u-mode? (normal trap OR debug-enter)
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csr.dcsr_rd(11) <= '0'; -- stepie: interrupts are disabled during single-stepping
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csr.dcsr_rd(11) <= '0'; -- stepie: interrupts are disabled during single-stepping
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csr.dcsr_rd(10) <= '0'; -- stopcount: counters increment as usual FIXME ???
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csr.dcsr_rd(10) <= '0'; -- stopcount: counters increment as usual FIXME/TODO ???
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csr.dcsr_rd(09) <= '0'; -- stoptime: timers increment as usual
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csr.dcsr_rd(09) <= '0'; -- stoptime: timers increment as usual FIXME/TODO ???
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csr.dcsr_rd(08 downto 06) <= csr.dcsr_cause; -- debug mode entry cause
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csr.dcsr_rd(08 downto 06) <= csr.dcsr_cause; -- debug mode entry cause
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csr.dcsr_rd(05) <= '0'; -- reserved
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csr.dcsr_rd(05) <= '0'; -- reserved
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csr.dcsr_rd(04) <= '0'; -- mprven: mstatus.mprv is ignored in debug mode
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csr.dcsr_rd(04) <= '0'; -- mprven: mstatus.mprv is ignored in debug mode
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csr.dcsr_rd(03) <= '0'; -- nmip: pending non-maskable interrupt
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csr.dcsr_rd(03) <= '0'; -- nmip: no pending non-maskable interrupt
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csr.dcsr_rd(02) <= csr.dcsr_step; -- step: single-step mode
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csr.dcsr_rd(02) <= csr.dcsr_step; -- step: single-step mode
|
csr.dcsr_rd(01 downto 00) <= csr.dcsr_prv; -- prv: privilege mode when debug mode was entered
|
csr.dcsr_rd(01 downto 00) <= csr.dcsr_prv; -- prv: privilege mode when debug mode was entered
|
end generate;
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|
|
|
|
|
end neorv32_cpu_control_rtl;
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end neorv32_cpu_control_rtl;
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No newline at end of file
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No newline at end of file
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