| Line 53... |
Line 53... |
-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
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-- Memory configuration: Instruction memory --
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-- Memory configuration: Instruction memory --
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MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
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MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
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MEM_ISPACE_SIZE : natural := 8*1024; -- total size of instruction memory space in byte
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MEM_ISPACE_SIZE : natural := 8*1024; -- total size of instruction memory space in byte
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MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
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MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
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MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
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MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
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Line 794... |
ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
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ctrl_nxt(ctrl_rf_wb_en_c) <= '1'; -- valid RF write-back
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--
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--
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execute_engine.is_jump_nxt <= '1'; -- this is a jump operation
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execute_engine.is_jump_nxt <= '1'; -- this is a jump operation
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execute_engine.state_nxt <= BRANCH;
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execute_engine.state_nxt <= BRANCH;
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when opcode_fence_c => -- fence operations
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-- ------------------------------------------------------------
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if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fencei_c) and (CPU_EXTENSION_RISCV_Zifencei = true) then -- FENCE.I
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fetch_engine.reset <= '1';
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execute_engine.pc_nxt <= execute_engine.next_pc;
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execute_engine.state_nxt <= SYS_WAIT;
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else
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execute_engine.state_nxt <= DISPATCH;
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end if;
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when opcode_syscsr_c => -- system/csr access
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when opcode_syscsr_c => -- system/csr access
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or
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if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrwi_c) then
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrwi_c) then
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csr.re_nxt <= not rd_is_r0_v; -- only read CSR if not writing to zero_reg
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csr.re_nxt <= not rd_is_r0_v; -- only read CSR if not writing to zero_reg
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Line 1033... |
illegal_instruction <= '1';
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illegal_instruction <= '1';
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else
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else
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illegal_instruction <= '0';
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illegal_instruction <= '0';
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end if;
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end if;
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when opcode_fence_c => -- fence instructions --
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if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fencei_c) and (CPU_EXTENSION_RISCV_Zifencei = true) then -- FENCE.I
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illegal_instruction <= '0';
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elsif (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_fence_c) then -- FENCE
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illegal_instruction <= '0';
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else
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illegal_instruction <= '1';
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end if;
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when opcode_syscsr_c => -- check system instructions --
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when opcode_syscsr_c => -- check system instructions --
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-- CSR access --
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-- CSR access --
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if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or
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if (execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrw_c) or
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrs_c) or
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrs_c) or
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrc_c) or
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(execute_engine.i_reg(instr_funct3_msb_c downto instr_funct3_lsb_c) = funct3_csrrc_c) or
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| Line 1381... |
Line 1401... |
csr_rdata_o(02) <= csr.misa_c_en; -- C CPU extension
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csr_rdata_o(02) <= csr.misa_c_en; -- C CPU extension
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csr_rdata_o(04) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- E CPU extension
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csr_rdata_o(04) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- E CPU extension
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csr_rdata_o(08) <= not bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- I CPU extension (if not E)
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csr_rdata_o(08) <= not bool_to_ulogic_f(CPU_EXTENSION_RISCV_E); -- I CPU extension (if not E)
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csr_rdata_o(12) <= csr.misa_m_en; -- M CPU extension
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csr_rdata_o(12) <= csr.misa_m_en; -- M CPU extension
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csr_rdata_o(23) <= '1'; -- X CPU extension: non-standard extensions
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csr_rdata_o(23) <= '1'; -- X CPU extension: non-standard extensions
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csr_rdata_o(25) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr); -- Z CPU extension
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csr_rdata_o(25) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr) and bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zifencei); -- Z CPU extension
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csr_rdata_o(30) <= '1'; -- 32-bit architecture (MXL lo)
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csr_rdata_o(30) <= '1'; -- 32-bit architecture (MXL lo)
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csr_rdata_o(31) <= '0'; -- 32-bit architecture (MXL hi)
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csr_rdata_o(31) <= '0'; -- 32-bit architecture (MXL hi)
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when x"304" => -- R/W: mie - machine interrupt-enable register
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when x"304" => -- R/W: mie - machine interrupt-enable register
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csr_rdata_o(03) <= csr.mie_msie; -- software IRQ enable
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csr_rdata_o(03) <= csr.mie_msie; -- software IRQ enable
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csr_rdata_o(07) <= csr.mie_mtie; -- timer IRQ enable
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csr_rdata_o(07) <= csr.mie_mtie; -- timer IRQ enable
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