| Line 75... |
Line 75... |
end record;
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end record;
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signal control : control_t;
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signal control : control_t;
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begin
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begin
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-- ****************************************************************************************************************************
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-- This controller is required to handle the CPU/pipeline interface. Do not modify!
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-- ****************************************************************************************************************************
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-- CFU Controller -------------------------------------------------------------------------
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-- CFU Controller -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- This controller is required to handle the CPU/pipeline interface. Do not modify!
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cfu_control: process(rstn_i, clk_i)
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cfu_control: process(rstn_i, clk_i)
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begin
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begin
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if (rstn_i = '0') then
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if (rstn_i = '0') then
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res_o <= (others => '0');
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res_o <= (others => '0');
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control.busy <= '0';
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control.busy <= '0';
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| Line 107... |
Line 110... |
control.funct3 <= ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c);
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control.funct3 <= ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c);
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control.funct7 <= ctrl_i(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_5_c);
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control.funct7 <= ctrl_i(ctrl_ir_funct12_11_c downto ctrl_ir_funct12_5_c);
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-- ****************************************************************************************************************************
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-- ****************************************************************************************************************************
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-- Actual CFU user logic - Add your custom logic below
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-- Actual CFU user logic - ADD YOUR CUSTOM LOGIC BELOW
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-- ****************************************************************************************************************************
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-- ****************************************************************************************************************************
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-- ----------------------------------------------------------------------------------------
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-- CFU Instruction Format
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-- ----------------------------------------------------------------------------------------
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-- The CFU only supports the R2-type RISC-V instruction format. This format consists of two source registers (rs1 and rs2),
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-- The CFU only supports the R2-type RISC-V instruction format. This format consists of two source registers (rs1 and rs2),
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-- a destination register (rd) and two "immediate" bit-fields (funct7 and funct3). It is up to the user to decide which
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-- a destination register (rd) and two "immediate" bit-fields (funct7 and funct3). It is up to the user to decide which
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-- of these fields are actually used by the CFU logic.
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-- of these fields are actually used by the CFU logic.
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--
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-- The user logic of the CFU has access to the following pre-defined signals:
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--
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-- ----------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- Input Operands
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-- Input Operands
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-- -------------------------------------------------------------------------------------------
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-- ----------------------------------------------------------------------------------------
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-- > rs1_i (input, 32-bit): source register 1
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-- > rs1_i (input, 32-bit): source register 1
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-- > rs2_i (input, 32-bit): source register 2
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-- > rs2_i (input, 32-bit): source register 2
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-- > control.funct3 (input, 3-bit): 3-bit function select / immediate, driven by instruction word's funct3 bit field
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-- > control.funct3 (input, 3-bit): 3-bit function select / immediate, driven by instruction word's funct3 bit field
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-- > control.funct7 (input, 7-bit): 7-bit function select / immediate, driven by instruction word's funct7 bit field
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-- > control.funct7 (input, 7-bit): 7-bit function select / immediate, driven by instruction word's funct7 bit field
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--
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--
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| Line 132... |
Line 137... |
-- The actual CFU operation can be defined by using the funct3 and funct7 signals. Both signals are directly driven by
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-- The actual CFU operation can be defined by using the funct3 and funct7 signals. Both signals are directly driven by
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-- the according bit-fields of the custom instruction. Note that these signals represent "immediates" that have to be
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-- the according bit-fields of the custom instruction. Note that these signals represent "immediates" that have to be
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-- static already at compile time. These immediates can be used to select the actual function to be executed or they
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-- static already at compile time. These immediates can be used to select the actual function to be executed or they
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-- can be used as immediates for certain operations (like shift amounts, addresses or offsets).
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-- can be used as immediates for certain operations (like shift amounts, addresses or offsets).
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--
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--
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-- [NOTE]: rs1_i and rs2_i are directly driven by the register file (block RAM). It is recommended to buffer these signals
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-- [NOTE] rs1_i and rs2_i are directly driven by the register file (block RAM). For complex CFU designs it is recommended
|
-- using CFU-internal registers before using them for computations as the rs1 and rs2 nets need to drive a lot of logic
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-- to buffer these signals using CFU-internal registers before using them for computations as the rs1 and rs2 nets
|
-- in the CPU.
|
-- need to drive a lot of logic in the CPU. Obviously, this will increase the CFU latency by one cycle.
|
--
|
--
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-- [NOTE]: It is not possible for the CFU and it's according instruction words to cause any kind of exception. The CPU
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-- [NOTE] It is not possible for the CFU and it's according instruction words to cause any kind of exception. The CPU
|
-- control logic only verifies the custom instructions OPCODE and checks if the CFU is implemented at all. No combination
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-- control logic only verifies the custom instructions OPCODE and checks if the CFU is implemented at all. No
|
-- of funct7 and funct3 will cause an exception.
|
-- combinations of funct7 and funct3 will cause an exception.
|
--
|
|
-- -------------------------------------------------------------------------------------------
|
|
-- Result output
|
-- ----------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- Result Output
|
|
-- ----------------------------------------------------------------------------------------
|
-- > control.result (output, 32-bit): processing result
|
-- > control.result (output, 32-bit): processing result
|
--
|
--
|
-- When the CFU has finished computation, the data in the control.result signal will be written to the CPU's register
|
-- When the CFU has finished computation, the data in the control.result signal will be written to the CPU's register
|
-- file. The destination register is addressed by the rd bit-field in the instruction. The CFU result output is
|
-- file. The destination register is addressed by the rd bit-field in the instruction. The CFU result output is
|
-- registered in the CFU controller (see above) so do not worry too much about increasing the CPU's critical path. ;)
|
-- registered in the CFU controller (see above) so do not worry too much about increasing the CPU's critical path. ;)
|
--
|
|
-- -------------------------------------------------------------------------------------------
|
|
|
-- ----------------------------------------------------------------------------------------
|
-- Control
|
-- Control
|
-- -------------------------------------------------------------------------------------------
|
-- ----------------------------------------------------------------------------------------
|
-- > rstn_i (input, 1-bit): asynchronous reset, low-active
|
-- > rstn_i (input, 1-bit): asynchronous reset, low-active
|
-- > clk_i (input, 1-bit): main clock, triggering on rising edge
|
-- > clk_i (input, 1-bit): main clock, triggering on rising edge
|
-- > start_i (input, 1-bit): operation trigger (start processing, high for one cycle)
|
-- > start_i (input, 1-bit): operation trigger (start processing, high for one cycle)
|
-- > control.done (output, 1-bit): set high when processing is done
|
-- > control.done (output, 1-bit): set high when processing is done
|
--
|
--
|
-- For pure-combinatorial instructions (without internal state) a subset of those signals is sufficient; see the minimal
|
-- For pure-combinatorial instructions (without internal state) a subset of those signals is sufficient; see the minimal
|
-- example below. If the CFU shall also include states (like memories, registers or "buffers") the start_i signal can be
|
-- example below. If the CFU shall also include states (like memories, registers or "buffers") the start_i signal can be
|
-- used to trigger a new CFU operation. As soon as all internal computations have completed, the control.done signal has
|
-- used to trigger a new CFU operation. As soon as all internal computations have completed, the control.done signal has
|
-- to be set to indicate completion. This will write the result data (control.result) to the CPU register file.
|
-- to be set to indicate completion. This will finish CFU operation and will write the processing result (control.result)
|
|
-- to the CPU register file.
|
--
|
--
|
-- [IMPORTANT]: The control.done *has to be set at some time*, otherwise the CPU will be halted forever.
|
-- [NOTE] The control.done **has to be set at some time**, otherwise the CPU will get stalled forever.
|
|
|
|
|
-- User Logic Example ---------------------------------------------------------------------
|
-- User Logic Example ---------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
user_logic_function_select: process(control, rs1_i, rs2_i)
|
user_logic_function_select: process(control, rs1_i, rs2_i)
|
