| Line 311... |
Line 311... |
variable op_m_all_zero_v, op_e_all_zero_v, op_e_all_one_v : std_ulogic;
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variable op_m_all_zero_v, op_e_all_zero_v, op_e_all_one_v : std_ulogic;
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variable op_is_zero_v, op_is_inf_v, op_is_denorm_v, op_is_nan_v : std_ulogic;
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variable op_is_zero_v, op_is_inf_v, op_is_denorm_v, op_is_nan_v : std_ulogic;
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begin
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begin
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for i in 0 to 1 loop -- for rs1 and rs2 inputs
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for i in 0 to 1 loop -- for rs1 and rs2 inputs
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-- check for all-zero/all-one --
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-- check for all-zero/all-one --
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op_m_all_zero_v := not or_all_f(op_data(i)(22 downto 00));
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op_m_all_zero_v := not or_reduce_f(op_data(i)(22 downto 00));
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op_e_all_zero_v := not or_all_f(op_data(i)(30 downto 23));
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op_e_all_zero_v := not or_reduce_f(op_data(i)(30 downto 23));
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op_e_all_one_v := and_all_f(op_data(i)(30 downto 23));
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op_e_all_one_v := and_reduce_f(op_data(i)(30 downto 23));
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-- check special cases --
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-- check special cases --
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op_is_zero_v := op_e_all_zero_v and op_m_all_zero_v; -- zero
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op_is_zero_v := op_e_all_zero_v and op_m_all_zero_v; -- zero
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op_is_inf_v := op_e_all_one_v and op_m_all_zero_v; -- infinity
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op_is_inf_v := op_e_all_one_v and op_m_all_zero_v; -- infinity
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op_is_denorm_v := '0'; -- FIXME / TODO -- op_e_all_zero_v and (not op_m_all_zero_v); -- subnormal
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op_is_denorm_v := '0'; -- FIXME / TODO -- op_e_all_zero_v and (not op_m_all_zero_v); -- subnormal
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| Line 1358... |
Line 1358... |
sreg.upper(31 downto 02) <= (others => '0');
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sreg.upper(31 downto 02) <= (others => '0');
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sreg.upper(01 downto 00) <= mantissa_i(47 downto 46);
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sreg.upper(01 downto 00) <= mantissa_i(47 downto 46);
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sreg.lower <= mantissa_i(45 downto 23);
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sreg.lower <= mantissa_i(45 downto 23);
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sreg.ext_g <= mantissa_i(22);
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sreg.ext_g <= mantissa_i(22);
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sreg.ext_r <= mantissa_i(21);
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sreg.ext_r <= mantissa_i(21);
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sreg.ext_s <= or_all_f(mantissa_i(20 downto 0));
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sreg.ext_s <= or_reduce_f(mantissa_i(20 downto 0));
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-- check for special cases --
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-- check for special cases --
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if ((ctrl.class(fp_class_snan_c) or ctrl.class(fp_class_qnan_c) or -- NaN
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if ((ctrl.class(fp_class_snan_c) or ctrl.class(fp_class_qnan_c) or -- NaN
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ctrl.class(fp_class_neg_zero_c) or ctrl.class(fp_class_pos_zero_c) or -- zero
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ctrl.class(fp_class_neg_zero_c) or ctrl.class(fp_class_pos_zero_c) or -- zero
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ctrl.class(fp_class_neg_denorm_c) or ctrl.class(fp_class_pos_denorm_c) or -- subnormal
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ctrl.class(fp_class_neg_denorm_c) or ctrl.class(fp_class_pos_denorm_c) or -- subnormal
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ctrl.class(fp_class_neg_inf_c) or ctrl.class(fp_class_pos_inf_c) or -- infinity
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ctrl.class(fp_class_neg_inf_c) or ctrl.class(fp_class_pos_inf_c) or -- infinity
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Line 1473... |
end case;
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end case;
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end if;
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end if;
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end process ctrl_engine;
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end process ctrl_engine;
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-- stop shifting when normalized --
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-- stop shifting when normalized --
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sreg.done <= (not or_all_f(sreg.upper(sreg.upper'left downto 1))) and sreg.upper(0); -- input is zero, hidden one is set
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sreg.done <= (not or_reduce_f(sreg.upper(sreg.upper'left downto 1))) and sreg.upper(0); -- input is zero, hidden one is set
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-- all-zero including hidden bit --
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-- all-zero including hidden bit --
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sreg.zero <= not or_all_f(sreg.upper);
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sreg.zero <= not or_reduce_f(sreg.upper);
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-- result --
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-- result --
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result_o(31) <= ctrl.res_sgn;
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result_o(31) <= ctrl.res_sgn;
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result_o(30 downto 23) <= ctrl.res_exp;
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result_o(30 downto 23) <= ctrl.res_exp;
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result_o(22 downto 0) <= ctrl.res_man;
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result_o(22 downto 0) <= ctrl.res_man;
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Line 1715... |
ctrl.state <= S_NORMALIZE_BUSY;
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ctrl.state <= S_NORMALIZE_BUSY;
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end if;
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end if;
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when S_NORMALIZE_BUSY => -- running normalization cycle
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when S_NORMALIZE_BUSY => -- running normalization cycle
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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sreg.ext_s <= sreg.ext_s or or_all_f(sreg.mant(sreg.mant'left-2 downto 0)); -- sticky bit
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sreg.ext_s <= sreg.ext_s or or_reduce_f(sreg.mant(sreg.mant'left-2 downto 0)); -- sticky bit
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if (or_all_f(ctrl.cnt(ctrl.cnt'left-1 downto 0)) = '0') then
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if (or_reduce_f(ctrl.cnt(ctrl.cnt'left-1 downto 0)) = '0') then
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if (ctrl.unsign = '0') then -- signed conversion
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if (ctrl.unsign = '0') then -- signed conversion
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ctrl.over <= ctrl.over or sreg.int(sreg.int'left); -- update overrun flag again to check for numerical overflow into sign bit
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ctrl.over <= ctrl.over or sreg.int(sreg.int'left); -- update overrun flag again to check for numerical overflow into sign bit
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end if;
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end if;
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ctrl.state <= S_ROUND;
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ctrl.state <= S_ROUND;
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else -- shift left
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else -- shift left
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