| Line 58... |
Line 58... |
);
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);
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end neorv32_cpu_cp_muldiv;
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end neorv32_cpu_cp_muldiv;
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architecture neorv32_cpu_cp_muldiv_rtl of neorv32_cpu_cp_muldiv is
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architecture neorv32_cpu_cp_muldiv_rtl of neorv32_cpu_cp_muldiv is
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-- constants --
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-- configuration - still experimental --
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constant all_zero_c : std_ulogic_vector(data_width_c-1 downto 0) := (others => '0');
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constant FAST_MUL_EN : boolean := false; -- use DSPs for faster multiplication
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-- controller --
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-- controller --
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type state_t is (IDLE, DECODE, INIT_OPX, INIT_OPY, PROCESSING, FINALIZE, COMPLETED);
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type state_t is (IDLE, DECODE, INIT_OPX, INIT_OPY, PROCESSING, FINALIZE, COMPLETED);
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signal state : state_t;
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signal state : state_t;
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signal cnt : std_ulogic_vector(4 downto 0);
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signal cnt : std_ulogic_vector(4 downto 0);
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| Line 84... |
Line 84... |
signal div_sign_comp : std_ulogic_vector(data_width_c-1 downto 0);
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signal div_sign_comp : std_ulogic_vector(data_width_c-1 downto 0);
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signal div_res : std_ulogic_vector(data_width_c-1 downto 0);
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signal div_res : std_ulogic_vector(data_width_c-1 downto 0);
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-- multiplier core --
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-- multiplier core --
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signal mul_product : std_ulogic_vector(63 downto 0);
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signal mul_product : std_ulogic_vector(63 downto 0);
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signal mul_do_add : std_ulogic_vector(32 downto 0);
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signal mul_do_add : std_ulogic_vector(data_width_c downto 0);
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signal mul_sign_cycle : std_ulogic;
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signal mul_sign_cycle : std_ulogic;
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signal mul_p_sext : std_ulogic;
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signal mul_p_sext : std_ulogic;
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signal mul_op_x : std_ulogic_vector(32 downto 0);
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signal mul_op_y : std_ulogic_vector(32 downto 0);
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signal mul_buf_ff0 : std_ulogic_vector(65 downto 0);
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signal mul_buf_ff1 : std_ulogic_vector(65 downto 0);
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begin
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begin
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-- Co-Processor Controller ----------------------------------------------------------------
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-- Co-Processor Controller ----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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| Line 120... |
Line 124... |
if (ctrl_i(ctrl_cp_use_c) = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = cp_sel_muldiv_c) then
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if (ctrl_i(ctrl_cp_use_c) = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = cp_sel_muldiv_c) then
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state <= DECODE;
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state <= DECODE;
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end if;
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end if;
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when DECODE =>
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when DECODE =>
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cnt <= "11111";
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--
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if (cp_op = cp_op_div_c) then -- result sign compensation for div?
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if (cp_op = cp_op_div_c) then -- result sign compensation for div?
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div_res_corr <= opx(opx'left) xor opy(opy'left);
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div_res_corr <= opx(opx'left) xor opy(opy'left);
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elsif (cp_op = cp_op_rem_c) then -- result sign compensation for rem?
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elsif (cp_op = cp_op_rem_c) then -- result sign compensation for rem?
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div_res_corr <= opx(opx'left);
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div_res_corr <= opx(opx'left);
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else
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else
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div_res_corr <= '0';
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div_res_corr <= '0';
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end if;
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end if;
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-- if (cp_op = cp_op_div_c) and (opy = all_zero_c) then -- *divide* by 0?
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--
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if (opy = all_zero_c) then -- *divide* by 0?
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if (or_all_f(opy) = '0') then -- *divide* by 0?
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opy_is_zero <= '1';
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opy_is_zero <= '1';
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else
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else
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opy_is_zero <= '0';
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opy_is_zero <= '0';
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end if;
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end if;
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--
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if (operation = '1') then -- division
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if (operation = '1') then -- division
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cnt <= "11111";
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state <= INIT_OPX;
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state <= INIT_OPX;
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else -- multiplication
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else -- multiplication
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if (FAST_MUL_EN = false) then
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cnt <= "11111";
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else
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cnt <= "00101"; -- FIXME
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end if;
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start <= '1';
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start <= '1';
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state <= PROCESSING;
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state <= PROCESSING;
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end if;
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end if;
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when INIT_OPX =>
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when INIT_OPX =>
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| Line 180... |
Line 191... |
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-- opy (rs2) signed? --
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-- opy (rs2) signed? --
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opy_is_signed <= '1' when (cp_op = cp_op_mulh_c) or (cp_op = cp_op_div_c) or (cp_op = cp_op_rem_c) else '0';
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opy_is_signed <= '1' when (cp_op = cp_op_mulh_c) or (cp_op = cp_op_div_c) or (cp_op = cp_op_rem_c) else '0';
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-- Multiplier Core ------------------------------------------------------------------------
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-- Multiplier Core (signed) ---------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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multiplier_core: process(clk_i)
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multiplier_core: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if (FAST_MUL_EN = false) then -- use small iterative computation
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if (start = '1') then -- start new multiplication
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if (start = '1') then -- start new multiplication
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mul_product(63 downto 32) <= (others => '0');
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mul_product(63 downto 32) <= (others => '0');
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mul_product(31 downto 00) <= opy;
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mul_product(31 downto 00) <= opy;
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elsif ((state = PROCESSING) or (state = FINALIZE)) and (operation = '0') then
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elsif ((state = PROCESSING) or (state = FINALIZE)) and (operation = '0') then
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mul_product(63 downto 31) <= mul_do_add(32 downto 0);
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mul_product(63 downto 31) <= mul_do_add(32 downto 0);
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mul_product(30 downto 00) <= mul_product(31 downto 1);
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mul_product(30 downto 00) <= mul_product(31 downto 1);
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end if;
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end if;
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else -- use direct approach using (several!) DSP blocks
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if (start = '1') then
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mul_op_x <= (opx(opx'left) and opx_is_signed) & opx;
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mul_op_y <= (opy(opy'left) and opy_is_signed) & opy;
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end if;
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mul_buf_ff0 <= std_ulogic_vector(signed(mul_op_x) * signed(mul_op_y));
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mul_buf_ff1 <= mul_buf_ff0;
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mul_product <= mul_buf_ff1(63 downto 0); -- let the register balancing do the magic here
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end if;
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end if;
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end if;
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end process multiplier_core;
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end process multiplier_core;
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-- MUL: do another addition --
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-- MUL: do another addition --
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mul_update: process(mul_product, mul_sign_cycle, mul_p_sext, opx_is_signed, opx)
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mul_update: process(mul_product, mul_sign_cycle, mul_p_sext, opx_is_signed, opx)
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begin
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begin
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if (mul_product(0) = '1') then
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-- current bit of opy to take care of --
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if (mul_sign_cycle = '1') then -- for signed operation only: take care of negative weighted MSB
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if (mul_product(0) = '1') then -- multiply with 1
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if (mul_sign_cycle = '1') then -- for signed operations only: take care of negative weighted MSB -> multiply with -1
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mul_do_add <= std_ulogic_vector(unsigned(mul_p_sext & mul_product(63 downto 32)) - unsigned((opx(opx'left) and opx_is_signed) & opx));
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mul_do_add <= std_ulogic_vector(unsigned(mul_p_sext & mul_product(63 downto 32)) - unsigned((opx(opx'left) and opx_is_signed) & opx));
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else
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else -- multiply with +1
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mul_do_add <= std_ulogic_vector(unsigned(mul_p_sext & mul_product(63 downto 32)) + unsigned((opx(opx'left) and opx_is_signed) & opx));
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mul_do_add <= std_ulogic_vector(unsigned(mul_p_sext & mul_product(63 downto 32)) + unsigned((opx(opx'left) and opx_is_signed) & opx));
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end if;
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end if;
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else
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else -- multiply with 0
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mul_do_add <= mul_p_sext & mul_product(63 downto 32);
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mul_do_add <= mul_p_sext & mul_product(63 downto 32);
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end if;
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end if;
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end process mul_update;
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end process mul_update;
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-- sign control --
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-- sign control --
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mul_sign_cycle <= opy_is_signed when (state = FINALIZE) else '0';
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mul_sign_cycle <= opy_is_signed when (state = FINALIZE) else '0';
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mul_p_sext <= mul_product(mul_product'left) and opx_is_signed;
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mul_p_sext <= mul_product(mul_product'left) and opx_is_signed;
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-- Divider Core ---------------------------------------------------------------------------
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-- Divider Core (unsigned) ----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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divider_core: process(clk_i)
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divider_core: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if (start = '1') then -- start new division
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if (start = '1') then -- start new division
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