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library neorv32;
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library neorv32;
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use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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entity neorv32_cpu_cp_muldiv is
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entity neorv32_cpu_cp_muldiv is
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generic (
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FAST_MUL_EN : boolean := false -- use DSPs for faster multiplication
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);
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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rstn_i : in std_ulogic; -- global reset, low-active, async
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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-- data input --
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-- data input --
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start_i : in std_ulogic; -- trigger operation
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rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
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rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
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rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
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rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
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-- result and status --
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-- result and status --
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res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
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res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
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valid_o : out std_ulogic -- data output valid
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valid_o : out std_ulogic -- data output valid
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);
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);
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end neorv32_cpu_cp_muldiv;
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end neorv32_cpu_cp_muldiv;
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architecture neorv32_cpu_cp_muldiv_rtl of neorv32_cpu_cp_muldiv is
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architecture neorv32_cpu_cp_muldiv_rtl of neorv32_cpu_cp_muldiv is
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-- configuration - still experimental --
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-- advanced configuration --
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constant FAST_MUL_EN : boolean := false; -- use DSPs for faster multiplication
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constant dsp_add_reg_stage_c : boolean := false; -- add another register stage to DSP-based multiplication for timing-closure
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-- controller --
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-- controller --
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type state_t is (IDLE, DECODE, INIT_OPX, INIT_OPY, PROCESSING, FINALIZE, COMPLETED);
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type state_t is (IDLE, DECODE, INIT_OPX, INIT_OPY, PROCESSING, FINALIZE, COMPLETED);
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signal state : state_t;
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signal state : state_t;
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signal cnt : std_ulogic_vector(4 downto 0);
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signal cnt : std_ulogic_vector(4 downto 0);
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-- multiplier core --
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-- multiplier core --
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signal mul_product : std_ulogic_vector(63 downto 0);
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signal mul_product : std_ulogic_vector(63 downto 0);
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signal mul_do_add : std_ulogic_vector(data_width_c downto 0);
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signal mul_do_add : std_ulogic_vector(data_width_c downto 0);
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signal mul_sign_cycle : std_ulogic;
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signal mul_sign_cycle : std_ulogic;
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signal mul_p_sext : std_ulogic;
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signal mul_p_sext : std_ulogic;
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signal mul_op_x : std_ulogic_vector(32 downto 0);
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signal mul_op_x : signed(32 downto 0); -- for using DSPs
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signal mul_op_y : std_ulogic_vector(32 downto 0);
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signal mul_op_y : signed(32 downto 0); -- for using DSPs
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signal mul_buf_ff0 : std_ulogic_vector(65 downto 0);
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signal mul_buf_ff : signed(65 downto 0); -- for using DSPs
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signal mul_buf_ff1 : std_ulogic_vector(65 downto 0);
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signal mul_buf2_ff : signed(65 downto 0); -- for using DSPs
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begin
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begin
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-- Co-Processor Controller ----------------------------------------------------------------
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-- Co-Processor Controller ----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- FSM --
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-- FSM --
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case state is
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case state is
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when IDLE =>
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when IDLE =>
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opx <= rs1_i;
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opx <= rs1_i;
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opy <= rs2_i;
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opy <= rs2_i;
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if (start_i = '1') then
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cp_op <= ctrl_i(ctrl_cp_cmd2_c downto ctrl_cp_cmd0_c);
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cp_op <= ctrl_i(ctrl_cp_cmd2_c downto ctrl_cp_cmd0_c);
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if (ctrl_i(ctrl_cp_use_c) = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = cp_sel_muldiv_c) then
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state <= DECODE;
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state <= DECODE;
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end if;
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end if;
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when DECODE =>
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when DECODE =>
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--
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--
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state <= INIT_OPX;
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state <= INIT_OPX;
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else -- multiplication
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else -- multiplication
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if (FAST_MUL_EN = false) then
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if (FAST_MUL_EN = false) then
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cnt <= "11111";
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cnt <= "11111";
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else
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else
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cnt <= "00101"; -- FIXME
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cnt <= "00001";
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end if;
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end if;
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start <= '1';
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start <= '1';
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state <= PROCESSING;
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state <= PROCESSING;
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end if;
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end if;
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mul_product(63 downto 31) <= mul_do_add(32 downto 0);
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mul_product(63 downto 31) <= mul_do_add(32 downto 0);
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mul_product(30 downto 00) <= mul_product(31 downto 1);
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mul_product(30 downto 00) <= mul_product(31 downto 1);
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end if;
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end if;
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else -- use direct approach using (several!) DSP blocks
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else -- use direct approach using (several!) DSP blocks
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if (start = '1') then
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if (start = '1') then
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mul_op_x <= (opx(opx'left) and opx_is_signed) & opx;
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mul_op_x <= signed((opx(opx'left) and opx_is_signed) & opx);
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mul_op_y <= (opy(opy'left) and opy_is_signed) & opy;
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mul_op_y <= signed((opy(opy'left) and opy_is_signed) & opy);
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end if;
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mul_buf_ff <= mul_op_x * mul_op_y;
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if (dsp_add_reg_stage_c = true) then -- add another reg stage?
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mul_buf2_ff <= mul_buf_ff;
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mul_product <= std_ulogic_vector(mul_buf2_ff(63 downto 0)); -- let the register balancing do the magic here
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else
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mul_product <= std_ulogic_vector(mul_buf_ff(63 downto 0)); -- let the register balancing do the magic here
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end if;
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end if;
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mul_buf_ff0 <= std_ulogic_vector(signed(mul_op_x) * signed(mul_op_y));
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mul_buf_ff1 <= mul_buf_ff0;
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mul_product <= mul_buf_ff1(63 downto 0); -- let the register balancing do the magic here
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end if;
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end if;
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end if;
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end if;
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end process multiplier_core;
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end process multiplier_core;
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-- MUL: do another addition --
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-- MUL: do another addition --
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