| Line 66... |
Line 66... |
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-- advanced configuration --
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-- advanced configuration --
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constant dsp_add_reg_stage_c : boolean := false; -- add another register stage to DSP-based multiplication for timing-closure
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constant dsp_add_reg_stage_c : boolean := false; -- add another register stage to DSP-based multiplication for timing-closure
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-- controller --
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-- controller --
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type state_t is (IDLE, DECODE, INIT_OPX, INIT_OPY, PROCESSING, FINALIZE, COMPLETED);
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type state_t is (IDLE, DECODE, INIT_OPX, INIT_OPY, PROCESSING, FINALIZE, COMPLETED, FAST_MUL);
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signal state : state_t;
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signal state : state_t;
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signal cnt : std_ulogic_vector(4 downto 0);
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signal cnt : std_ulogic_vector(4 downto 0);
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signal cp_op : std_ulogic_vector(2 downto 0); -- operation to execute
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signal cp_op : std_ulogic_vector(2 downto 0); -- operation to execute
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signal start : std_ulogic;
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signal start : std_ulogic;
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signal operation : std_ulogic;
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signal operation : std_ulogic;
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| Line 143... |
Line 143... |
opy_is_zero <= '1';
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opy_is_zero <= '1';
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else
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else
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opy_is_zero <= '0';
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opy_is_zero <= '0';
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end if;
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end if;
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--
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--
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if (operation = '1') then -- division
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cnt <= "11111";
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cnt <= "11111";
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if (operation = '1') then -- division
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state <= INIT_OPX;
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state <= INIT_OPX;
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else -- multiplication
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else -- multiplication
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if (FAST_MUL_EN = false) then
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cnt <= "11111";
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else
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cnt <= "00001";
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end if;
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start <= '1';
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start <= '1';
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if (FAST_MUL_EN = true) then
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state <= FAST_MUL;
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else
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state <= PROCESSING;
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state <= PROCESSING;
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end if;
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end if;
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end if;
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when INIT_OPX =>
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when INIT_OPX =>
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if ((opx(opx'left) and opx_is_signed) = '1') then -- signed division?
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if ((opx(opx'left) and opx_is_signed) = '1') then -- signed division?
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opx <= div_sign_comp; -- make positive
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opx <= div_sign_comp; -- make positive
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end if;
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end if;
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| Line 175... |
Line 174... |
cnt <= std_ulogic_vector(unsigned(cnt) - 1);
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cnt <= std_ulogic_vector(unsigned(cnt) - 1);
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if (cnt = "00000") then
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if (cnt = "00000") then
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state <= FINALIZE;
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state <= FINALIZE;
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end if;
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end if;
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when FAST_MUL =>
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state <= FINALIZE;
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when FINALIZE =>
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when FINALIZE =>
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state <= COMPLETED;
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state <= COMPLETED;
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when COMPLETED =>
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when COMPLETED =>
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valid_o <= '1';
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valid_o <= '1';
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