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-- # << NEORV32 - CPU Co-Processor: MULDIV unit >> #
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-- # << NEORV32 - CPU Co-Processor: MULDIV unit >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # Multiplier and Divider unit. Implements the RISC-V RV32-M CPU extension. #
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-- # Multiplier and Divider unit. Implements the RISC-V RV32-M CPU extension. #
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-- # Multiplier core (signed/unsigned) uses serial algorithm. -> 32+4 cycles latency #
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-- # Multiplier core (signed/unsigned) uses serial algorithm. -> 32+4 cycles latency #
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-- # Divider core (unsigned) uses serial algorithm. -> 32+6 cycles latency #
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-- # Divider core (unsigned) uses serial algorithm. -> 32+6 cycles latency #
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-- # Multiplications can be mapped to DSP block when FAST_MUL_EN = true. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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rstn_i : in std_ulogic; -- global reset, low-active, async
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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-- data input --
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start_i : in std_ulogic; -- trigger operation
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start_i : in std_ulogic; -- trigger operation
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-- data input --
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rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
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rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
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rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
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rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
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-- result and status --
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-- result and status --
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res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
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res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
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valid_o : out std_ulogic -- data output valid
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valid_o : out std_ulogic -- data output valid
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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coprocessor_ctrl: process(rstn_i, clk_i)
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coprocessor_ctrl: process(rstn_i, clk_i)
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begin
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begin
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if (rstn_i = '0') then
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if (rstn_i = '0') then
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state <= IDLE;
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state <= IDLE;
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cp_op <= (others => '0');
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opx <= (others => '0');
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opx <= (others => '0');
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opy <= (others => '0');
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opy <= (others => '0');
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cnt <= (others => '0');
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cnt <= (others => '0');
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start <= '0';
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start <= '0';
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valid_o <= '0';
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valid_o <= '0';
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case state is
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case state is
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when IDLE =>
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when IDLE =>
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opx <= rs1_i;
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opx <= rs1_i;
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opy <= rs2_i;
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opy <= rs2_i;
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if (start_i = '1') then
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if (start_i = '1') then
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cp_op <= ctrl_i(ctrl_cp_cmd2_c downto ctrl_cp_cmd0_c);
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state <= DECODE;
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state <= DECODE;
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end if;
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end if;
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when DECODE =>
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when DECODE =>
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--
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--
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state <= IDLE;
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state <= IDLE;
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end case;
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end case;
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end if;
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end if;
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end process coprocessor_ctrl;
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end process coprocessor_ctrl;
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-- co-processor command --
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cp_op <= ctrl_i(ctrl_ir_funct3_2_c downto ctrl_ir_funct3_0_c);
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-- operation --
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-- operation --
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operation <= '1' when (cp_op = cp_op_div_c) or (cp_op = cp_op_divu_c) or (cp_op = cp_op_rem_c) or (cp_op = cp_op_remu_c) else '0';
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operation <= '1' when (cp_op = cp_op_div_c) or (cp_op = cp_op_divu_c) or (cp_op = cp_op_rem_c) or (cp_op = cp_op_remu_c) else '0';
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-- opx (rs1) signed? --
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-- opx (rs1) signed? --
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opx_is_signed <= '1' when (cp_op = cp_op_mulh_c) or (cp_op = cp_op_mulhsu_c) or (cp_op = cp_op_div_c) or (cp_op = cp_op_rem_c) else '0';
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opx_is_signed <= '1' when (cp_op = cp_op_mulh_c) or (cp_op = cp_op_mulhsu_c) or (cp_op = cp_op_div_c) or (cp_op = cp_op_rem_c) else '0';
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-- opy (rs2) signed? --
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-- opy (rs2) signed? --
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opy_is_signed <= '1' when (cp_op = cp_op_mulh_c) or (cp_op = cp_op_div_c) or (cp_op = cp_op_rem_c) else '0';
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opy_is_signed <= '1' when (cp_op = cp_op_mulh_c) or (cp_op = cp_op_div_c) or (cp_op = cp_op_rem_c) else '0';
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-- Multiplier Core (signed) ---------------------------------------------------------------
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-- Multiplier Core (signed/unsigned) ------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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multiplier_core: process(clk_i)
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multiplier_core: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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-- ---------------------------------------------------------
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if (FAST_MUL_EN = false) then -- use small iterative computation
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if (FAST_MUL_EN = false) then -- use small iterative computation
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if (start = '1') then -- start new multiplication
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if (start = '1') then -- start new multiplication
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mul_product(63 downto 32) <= (others => '0');
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mul_product(63 downto 32) <= (others => '0');
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mul_product(31 downto 00) <= opy;
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mul_product(31 downto 00) <= opy;
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elsif ((state = PROCESSING) or (state = FINALIZE)) and (operation = '0') then
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elsif ((state = PROCESSING) or (state = FINALIZE)) and (operation = '0') then
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mul_product(63 downto 31) <= mul_do_add(32 downto 0);
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mul_product(63 downto 31) <= mul_do_add(32 downto 0);
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mul_product(30 downto 00) <= mul_product(31 downto 1);
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mul_product(30 downto 00) <= mul_product(31 downto 1);
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end if;
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end if;
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-- ---------------------------------------------------------
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else -- use direct approach using (several!) DSP blocks
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else -- use direct approach using (several!) DSP blocks
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if (start = '1') then
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if (start = '1') then
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mul_op_x <= signed((opx(opx'left) and opx_is_signed) & opx);
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mul_op_x <= signed((opx(opx'left) and opx_is_signed) & opx);
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mul_op_y <= signed((opy(opy'left) and opy_is_signed) & opy);
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mul_op_y <= signed((opy(opy'left) and opy_is_signed) & opy);
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end if;
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end if;
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