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-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - CPU Co-Processor: MULDIV unit >> #
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-- # << NEORV32 - CPU Co-Processor: MULDIV unit (RISC-V "M" Extension)>> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # Multiplier and Divider unit. Implements the RISC-V RV32-M CPU extension. #
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-- # Multiplier and Divider unit. Implements the RISC-V RV32-M CPU extension. #
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-- # Multiplier core (signed/unsigned) uses serial algorithm. -> 32+4 cycles latency #
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-- # Multiplier core (signed/unsigned) uses serial algorithm. -> 32+4 cycles latency #
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-- # Divider core (unsigned) uses serial algorithm. -> 32+6 cycles latency #
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-- # Divider core (unsigned) uses serial algorithm. -> 32+6 cycles latency #
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-- # Multiplications can be mapped to DSP block when FAST_MUL_EN = true. #
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-- # Multiplications can be mapped to DSP block when FAST_MUL_EN = true. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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architecture neorv32_cpu_cp_muldiv_rtl of neorv32_cpu_cp_muldiv is
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architecture neorv32_cpu_cp_muldiv_rtl of neorv32_cpu_cp_muldiv is
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-- advanced configuration --
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-- advanced configuration --
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constant dsp_add_reg_stage_c : boolean := false; -- add another register stage to DSP-based multiplication for timing-closure
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constant dsp_add_reg_stage_c : boolean := false; -- add another register stage to DSP-based multiplication for timing-closure
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-- operations --
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constant cp_op_mul_c : std_ulogic_vector(2 downto 0) := "000"; -- mul
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constant cp_op_mulh_c : std_ulogic_vector(2 downto 0) := "001"; -- mulh
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constant cp_op_mulhsu_c : std_ulogic_vector(2 downto 0) := "010"; -- mulhsu
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constant cp_op_mulhu_c : std_ulogic_vector(2 downto 0) := "011"; -- mulhu
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constant cp_op_div_c : std_ulogic_vector(2 downto 0) := "100"; -- div
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constant cp_op_divu_c : std_ulogic_vector(2 downto 0) := "101"; -- divu
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constant cp_op_rem_c : std_ulogic_vector(2 downto 0) := "110"; -- rem
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constant cp_op_remu_c : std_ulogic_vector(2 downto 0) := "111"; -- remu
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-- controller --
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-- controller --
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type state_t is (IDLE, DECODE, INIT_OPX, INIT_OPY, PROCESSING, FINALIZE, COMPLETED, FAST_MUL);
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type state_t is (IDLE, DECODE, INIT_OPX, INIT_OPY, PROCESSING, FINALIZE, COMPLETED, FAST_MUL);
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signal state : state_t;
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signal state : state_t;
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signal cnt : std_ulogic_vector(4 downto 0);
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signal cnt : std_ulogic_vector(4 downto 0);
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signal cp_op : std_ulogic_vector(2 downto 0); -- operation to execute
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signal cp_op : std_ulogic_vector(2 downto 0); -- operation to execute
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