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-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - CPU Co-Processor: Integer Multiplier/Divider Unit (RISC-V "M" Extension)>> #
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-- # << NEORV32 - CPU Co-Processor: Integer Multiplier/Divider Unit (RISC-V "M" Extension)>> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # Multiplier and Divider unit. Implements the RISC-V M CPU extension. #
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-- # Multiplier and Divider unit. Implements the RISC-V M CPU extension. #
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-- # #
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-- # #
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-- # Multiplier core (signed/unsigned) uses classical serial algorithm. Unit atency: 31+3 cycles #
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-- # Multiplier core (signed/unsigned) uses classical serial algorithm. Unit latency: 31+3 cycles #
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-- # Divider core (unsigned) uses classical serial algorithm. Unit latency: 32+4 cycles #
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-- # Divider core (unsigned) uses classical serial algorithm. Unit latency: 32+4 cycles #
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-- # #
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-- # #
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-- # Multiplications can be mapped to DSP blocks (faster!) when FAST_MUL_EN = true. #
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-- # Multiplications can be mapped to DSP blocks (faster!) when FAST_MUL_EN = true. #
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-- # Unit latency: 3 cycles #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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library neorv32;
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library neorv32;
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use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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entity neorv32_cpu_cp_muldiv is
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entity neorv32_cpu_cp_muldiv is
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generic (
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generic (
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FAST_MUL_EN : boolean := false -- use DSPs for faster multiplication
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FAST_MUL_EN : boolean := false; -- use DSPs for faster multiplication
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DIVISION_EN : boolean := true -- implement divider hardware
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);
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);
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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rstn_i : in std_ulogic; -- global reset, low-active, async
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signal div_sign_comp_in : std_ulogic_vector(data_width_c-1 downto 0);
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signal div_sign_comp_in : std_ulogic_vector(data_width_c-1 downto 0);
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signal div_sign_comp : std_ulogic_vector(data_width_c-1 downto 0);
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signal div_sign_comp : std_ulogic_vector(data_width_c-1 downto 0);
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signal div_res : std_ulogic_vector(data_width_c-1 downto 0);
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signal div_res : std_ulogic_vector(data_width_c-1 downto 0);
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-- multiplier core --
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-- multiplier core --
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signal mul_product_p : std_ulogic_vector(63 downto 0);
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signal mul_product_s : std_ulogic_vector(63 downto 0);
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signal mul_product : std_ulogic_vector(63 downto 0);
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signal mul_product : std_ulogic_vector(63 downto 0);
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signal mul_do_add : std_ulogic_vector(data_width_c downto 0);
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signal mul_do_add : std_ulogic_vector(data_width_c downto 0);
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signal mul_sign_cycle : std_ulogic;
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signal mul_sign_cycle : std_ulogic;
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signal mul_p_sext : std_ulogic;
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signal mul_p_sext : std_ulogic;
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signal mul_op_x : signed(32 downto 0); -- for using DSPs
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signal mul_op_x : signed(32 downto 0); -- for using DSPs
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-- FSM --
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-- FSM --
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case state is
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case state is
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when IDLE =>
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when IDLE =>
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cp_op_ff <= cp_op;
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cp_op_ff <= cp_op;
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if (start_i = '1') then
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if (start_i = '1') then
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if (operation = '1') then -- division
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if (operation = '1') and (DIVISION_EN = true) then -- division
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cnt <= "11111";
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cnt <= "11111";
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state <= DIV_PREPROCESS;
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state <= DIV_PREPROCESS;
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else
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else
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cnt <= "11110";
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cnt <= "11110";
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if (FAST_MUL_EN = true) then
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if (FAST_MUL_EN = true) then
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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when DIV_PREPROCESS =>
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when DIV_PREPROCESS =>
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if (DIVISION_EN = true) then
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-- check rlevatn input signs --
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-- check rlevatn input signs --
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if (cp_op = cp_op_div_c) then -- result sign compensation for div?
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if (cp_op = cp_op_div_c) then -- result sign compensation for div?
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div_res_corr <= rs1_i(rs1_i'left) xor rs2_i(rs2_i'left);
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div_res_corr <= rs1_i(rs1_i'left) xor rs2_i(rs2_i'left);
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elsif (cp_op = cp_op_rem_c) then -- result sign compensation for rem?
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elsif (cp_op = cp_op_rem_c) then -- result sign compensation for rem?
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div_res_corr <= rs1_i(rs1_i'left);
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div_res_corr <= rs1_i(rs1_i'left);
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div_opy <= rs2_i;
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div_opy <= rs2_i;
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end if;
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end if;
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--
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--
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start_div <= '1';
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start_div <= '1';
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state <= PROCESSING;
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state <= PROCESSING;
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else
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state <= IDLE;
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end if;
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when PROCESSING =>
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when PROCESSING =>
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cnt <= std_ulogic_vector(unsigned(cnt) - 1);
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cnt <= std_ulogic_vector(unsigned(cnt) - 1);
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if (cnt = "00000") then
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if (cnt = "00000") then
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state <= FINALIZE;
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state <= FINALIZE;
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start_mul <= '1' when (state = IDLE) and (start_i = '1') and (operation = '0') else '0';
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start_mul <= '1' when (state = IDLE) and (start_i = '1') and (operation = '0') else '0';
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-- Multiplier Core (signed/unsigned) ------------------------------------------------------
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-- Multiplier Core (signed/unsigned) ------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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multiplier_core_serial: process(rstn_i, clk_i)
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-- iterative multiplication (bit-serial) --
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multiplier_core_serial:
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if (FAST_MUL_EN = false) generate
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multiplier_core: process(rstn_i, clk_i)
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begin
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begin
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if (rstn_i = '0') then
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if (rstn_i = '0') then
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mul_product_s <= (others => def_rst_val_c);
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mul_product <= (others => def_rst_val_c);
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elsif rising_edge(clk_i) then
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elsif rising_edge(clk_i) then
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if (FAST_MUL_EN = false) then -- use small iterative computation
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if (start_mul = '1') then -- start new multiplication
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if (start_mul = '1') then -- start new multiplication
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mul_product_s(63 downto 32) <= (others => '0');
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mul_product(63 downto 32) <= (others => '0');
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mul_product_s(31 downto 00) <= rs2_i;
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mul_product(31 downto 00) <= rs2_i;
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elsif (state = PROCESSING) or (state = FINALIZE) then -- processing step or sign-finalization step
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elsif (state = PROCESSING) or (state = FINALIZE) then -- processing step or sign-finalization step
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mul_product_s(63 downto 31) <= mul_do_add(32 downto 0);
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mul_product(63 downto 31) <= mul_do_add(32 downto 0);
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mul_product_s(30 downto 00) <= mul_product_s(31 downto 1);
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mul_product(30 downto 00) <= mul_product(31 downto 1);
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end if;
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end if;
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end if;
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end if;
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end if;
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end process multiplier_core;
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end process multiplier_core_serial;
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end generate;
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multiplier_core_dsp: process(clk_i)
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-- parallel multiplication --
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multiplier_core_dsp:
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if (FAST_MUL_EN = true) generate
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multiplier_core: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if (FAST_MUL_EN = true) then -- use direct approach using DSP blocks
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if (start_mul = '1') then
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if (start_mul = '1') then
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mul_op_x <= signed((rs1_i(rs1_i'left) and rs1_is_signed) & rs1_i);
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mul_op_x <= signed((rs1_i(rs1_i'left) and rs1_is_signed) & rs1_i);
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mul_op_y <= signed((rs2_i(rs2_i'left) and rs2_is_signed) & rs2_i);
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mul_op_y <= signed((rs2_i(rs2_i'left) and rs2_is_signed) & rs2_i);
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end if;
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end if;
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mul_buf_ff <= mul_op_x * mul_op_y;
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mul_buf_ff <= mul_op_x * mul_op_y;
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mul_product_p <= std_ulogic_vector(mul_buf_ff(63 downto 0)); -- let the register balancing do the magic here
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mul_product <= std_ulogic_vector(mul_buf_ff(63 downto 0)); -- let the register balancing do the magic here
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end if;
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end if;
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end if;
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end process multiplier_core_dsp;
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end process multiplier_core;
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end generate;
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mul_product <= mul_product_p when (FAST_MUL_EN = true) else mul_product_s;
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-- do another addition (bit-serial) --
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-- do another addition --
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mul_update: process(mul_product, mul_sign_cycle, mul_p_sext, rs1_is_signed, rs1_i)
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mul_update: process(mul_product, mul_sign_cycle, mul_p_sext, rs1_is_signed, rs1_i)
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begin
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begin
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-- current bit of rs2_i to take care of --
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-- current bit of rs2_i to take care of --
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if (mul_product(0) = '1') then -- multiply with 1
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if (mul_product(0) = '1') then -- multiply with 1
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if (mul_sign_cycle = '1') then -- for signed operations only: take care of negative weighted MSB -> multiply with -1
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if (mul_sign_cycle = '1') then -- for signed operations only: take care of negative weighted MSB -> multiply with -1
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mul_p_sext <= mul_product(mul_product'left) and rs1_is_signed;
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mul_p_sext <= mul_product(mul_product'left) and rs1_is_signed;
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-- Divider Core (unsigned) ----------------------------------------------------------------
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-- Divider Core (unsigned) ----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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divider_core_serial:
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if (DIVISION_EN = true) generate
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divider_core: process(rstn_i, clk_i)
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divider_core: process(rstn_i, clk_i)
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begin
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begin
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if (rstn_i = '0') then
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if (rstn_i = '0') then
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quotient <= (others => def_rst_val_c);
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quotient <= (others => def_rst_val_c);
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remainder <= (others => def_rst_val_c);
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remainder <= (others => def_rst_val_c);
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-- result sign compensation --
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-- result sign compensation --
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div_sign_comp_in <= quotient when (cp_op = cp_op_div_c) else remainder;
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div_sign_comp_in <= quotient when (cp_op = cp_op_div_c) else remainder;
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div_sign_comp <= std_ulogic_vector(0 - unsigned(div_sign_comp_in));
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div_sign_comp <= std_ulogic_vector(0 - unsigned(div_sign_comp_in));
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div_res <= div_sign_comp when (div_res_corr = '1') and (opy_is_zero = '0') else div_sign_comp_in;
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div_res <= div_sign_comp when (div_res_corr = '1') and (opy_is_zero = '0') else div_sign_comp_in;
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end generate;
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-- no divider --
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divider_core_serial_none:
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if (DIVISION_EN = false) generate
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remainder <= (others => '-');
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quotient <= (others => '-');
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div_res <= (others => '-');
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end generate;
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-- Data Output ----------------------------------------------------------------------------
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-- Data Output ----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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operation_result: process(rstn_i, clk_i)
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operation_result: process(rstn_i, clk_i)
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Line 326... |
when cp_op_mul_c =>
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when cp_op_mul_c =>
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res_o <= mul_product(31 downto 00);
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res_o <= mul_product(31 downto 00);
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when cp_op_mulh_c | cp_op_mulhsu_c | cp_op_mulhu_c =>
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when cp_op_mulh_c | cp_op_mulhsu_c | cp_op_mulhu_c =>
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res_o <= mul_product(63 downto 32);
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res_o <= mul_product(63 downto 32);
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when cp_op_div_c =>
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when cp_op_div_c =>
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res_o <= div_res;
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if (DIVISION_EN = true) then res_o <= div_res; else NULL; end if;
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when cp_op_divu_c =>
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when cp_op_divu_c =>
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res_o <= quotient;
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if (DIVISION_EN = true) then res_o <= quotient; else NULL; end if;
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when cp_op_rem_c =>
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when cp_op_rem_c =>
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if (DIVISION_EN = true) then
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if (opy_is_zero = '0') then
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if (opy_is_zero = '0') then
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res_o <= div_res;
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res_o <= div_res;
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else
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else
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res_o <= rs1_i;
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res_o <= rs1_i;
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end if;
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end if;
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else
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NULL;
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end if;
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when others => -- cp_op_remu_c
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when others => -- cp_op_remu_c
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res_o <= remainder;
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if (DIVISION_EN = true) then res_o <= remainder; else NULL; end if;
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end process operation_result;
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end process operation_result;
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