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-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - CPU Co-Processor: Integer Multiplier/Divider Unit (RISC-V "M" Extension) >> #
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-- # << NEORV32 - CPU Co-Processor: Integer Multiplier/Divider Unit (RISC-V "M" Extension) >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # Multiplier and Divider unit. Implements the RISC-V M CPU extension. #
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-- # Multiplier and Divider unit. Implements the RISC-V M & Zmmul CPU extensions. #
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-- # #
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-- # Multiplier core (signed/unsigned) uses classical serial algorithm. Unit latency: 31+3 cycles #
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-- # Divider core (unsigned) uses classical serial algorithm. Unit latency: 32+4 cycles #
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-- # #
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-- # #
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-- # Multiplier core (signed/unsigned) uses classical serial algorithm. Latency = 31+3 cycles. #
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-- # Multiplications can be mapped to DSP blocks (faster!) when FAST_MUL_EN = true. #
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-- # Multiplications can be mapped to DSP blocks (faster!) when FAST_MUL_EN = true. #
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-- # Divider core (unsigned-only) uses classical serial algorithm. latency = 32+4 cycles. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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signal start_mul : std_ulogic;
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signal start_mul : std_ulogic;
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signal operation : std_ulogic;
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signal operation : std_ulogic;
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signal div_opy : std_ulogic_vector(data_width_c-1 downto 0);
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signal div_opy : std_ulogic_vector(data_width_c-1 downto 0);
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signal rs1_is_signed : std_ulogic;
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signal rs1_is_signed : std_ulogic;
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signal rs2_is_signed : std_ulogic;
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signal rs2_is_signed : std_ulogic;
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signal opy_is_zero : std_ulogic;
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signal div_res_corr : std_ulogic;
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signal div_res_corr : std_ulogic;
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signal out_en : std_ulogic;
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signal out_en : std_ulogic;
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-- divider core --
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-- divider core --
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signal remainder : std_ulogic_vector(data_width_c-1 downto 0);
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signal remainder : std_ulogic_vector(data_width_c-1 downto 0);
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cp_op_ff <= (others => def_rst_val_c);
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cp_op_ff <= (others => def_rst_val_c);
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start_div <= '0';
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start_div <= '0';
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out_en <= '0';
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out_en <= '0';
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valid_o <= '0';
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valid_o <= '0';
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div_res_corr <= def_rst_val_c;
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div_res_corr <= def_rst_val_c;
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opy_is_zero <= def_rst_val_c;
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elsif rising_edge(clk_i) then
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elsif rising_edge(clk_i) then
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-- defaults --
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-- defaults --
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start_div <= '0';
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start_div <= '0';
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out_en <= '0';
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out_en <= '0';
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valid_o <= '0';
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valid_o <= '0';
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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when DIV_PREPROCESS =>
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when DIV_PREPROCESS =>
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-- check relevant input signs --
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-- check relevant input signs for result sign compensation --
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if (cp_op = cp_op_div_c) then -- result sign compensation for div?
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if (cp_op = cp_op_div_c) then -- signed div operation
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div_res_corr <= rs1_i(rs1_i'left) xor rs2_i(rs2_i'left);
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div_res_corr <= (rs1_i(rs1_i'left) xor rs2_i(rs2_i'left)) and or_reduce_f(rs2_i); -- different signs AND rs2 not zero
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elsif (cp_op = cp_op_rem_c) then -- result sign compensation for rem?
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elsif (cp_op = cp_op_rem_c) then -- signed rem operation
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div_res_corr <= rs1_i(rs1_i'left);
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div_res_corr <= rs1_i(rs1_i'left);
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else
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else
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div_res_corr <= '0';
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div_res_corr <= '0';
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end if;
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end if;
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-- divide by zero? --
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opy_is_zero <= not or_reduce_f(rs2_i); -- set if rs2 = 0
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-- abs(rs2) --
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-- abs(rs2) --
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if ((rs2_i(rs2_i'left) and rs2_is_signed) = '1') then -- signed division?
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if ((rs2_i(rs2_i'left) and rs2_is_signed) = '1') then -- signed division?
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div_opy <= std_ulogic_vector(0 - unsigned(rs2_i)); -- make positive
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div_opy <= std_ulogic_vector(0 - unsigned(rs2_i)); -- make positive
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else
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else
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div_opy <= rs2_i;
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div_opy <= rs2_i;
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end if;
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end if;
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--
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state <= PROCESSING;
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state <= PROCESSING;
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when PROCESSING =>
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when PROCESSING =>
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cnt <= std_ulogic_vector(unsigned(cnt) - 1);
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cnt <= std_ulogic_vector(unsigned(cnt) - 1);
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if (cnt = "00000") or (ctrl_i(ctrl_trap_c) = '1') then -- abort on trap
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if (cnt = "00000") or (ctrl_i(ctrl_trap_c) = '1') then -- abort on trap
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-- try another subtraction --
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-- try another subtraction --
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div_sub <= std_ulogic_vector(unsigned('0' & remainder(30 downto 0) & quotient(31)) - unsigned('0' & div_opy));
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div_sub <= std_ulogic_vector(unsigned('0' & remainder(30 downto 0) & quotient(31)) - unsigned('0' & div_opy));
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-- result sign compensation --
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-- result sign compensation --
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div_sign_comp_in <= quotient when (cp_op = cp_op_div_c) else remainder;
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div_sign_comp_in <= quotient when (cp_op = cp_op_div_c) or (cp_op = cp_op_divu_c) else remainder;
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div_sign_comp <= std_ulogic_vector(0 - unsigned(div_sign_comp_in));
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div_sign_comp <= std_ulogic_vector(0 - unsigned(div_sign_comp_in));
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div_res <= div_sign_comp when (div_res_corr = '1') and (opy_is_zero = '0') else div_sign_comp_in;
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div_res <= div_sign_comp when (div_res_corr = '1') else div_sign_comp_in;
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end generate;
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end generate;
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-- no divider --
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-- no divider --
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divider_core_serial_none:
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divider_core_serial_none:
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if (DIVISION_EN = false) generate
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if (DIVISION_EN = false) generate
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remainder <= (others => '0');
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remainder <= (others => '0');
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quotient <= (others => '0');
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quotient <= (others => '0');
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div_sub <= (others => '0');
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div_sign_comp_in <= (others => '0');
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div_sign_comp <= (others => '0');
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div_res <= (others => '0');
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div_res <= (others => '0');
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end generate;
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end generate;
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-- Data Output ----------------------------------------------------------------------------
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-- Data Output ----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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operation_result: process(out_en, cp_op_ff, mul_product, div_res, quotient, opy_is_zero, rs1_i, remainder)
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operation_result: process(out_en, cp_op_ff, mul_product, div_res, div_sign_comp_in)
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begin
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begin
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if (out_en = '1') then
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if (out_en = '1') then
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case cp_op_ff is
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case cp_op_ff is
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when cp_op_mul_c =>
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when cp_op_mul_c =>
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res_o <= mul_product(31 downto 00);
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res_o <= mul_product(31 downto 00);
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when cp_op_mulh_c | cp_op_mulhsu_c | cp_op_mulhu_c =>
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when cp_op_mulh_c | cp_op_mulhsu_c | cp_op_mulhu_c =>
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res_o <= mul_product(63 downto 32);
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res_o <= mul_product(63 downto 32);
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when cp_op_div_c =>
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when cp_op_div_c | cp_op_rem_c =>
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res_o <= div_res;
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when cp_op_divu_c =>
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res_o <= quotient;
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when cp_op_rem_c =>
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if (opy_is_zero = '0') then
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res_o <= div_res;
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res_o <= div_res;
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else
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when others => -- cp_op_divu_c | cp_op_remu_c
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res_o <= rs1_i;
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res_o <= div_sign_comp_in;
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end if;
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when others => -- cp_op_remu_c
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res_o <= remainder;
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end case;
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end case;
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else
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else
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res_o <= (others => '0');
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res_o <= (others => '0');
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end if;
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end if;
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end process operation_result;
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end process operation_result;
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