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-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - CPU Register File >> #
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-- # << NEORV32 - CPU Register File >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # General purpose data registers. 32 entries for normal mode, 16 entries for embedded mode when #
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-- # General purpose data registers. 32 entries for normal mode, 16 entries for embedded mode when #
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-- # RISC-V M extension is enabled. R0 output is hardwired to zero. #
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-- # RISC-V M extension is enabled. x0 output is allways set to zero. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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type reg_file_t is array (31 downto 0) of std_ulogic_vector(data_width_c-1 downto 0);
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type reg_file_t is array (31 downto 0) of std_ulogic_vector(data_width_c-1 downto 0);
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type reg_file_emb_t is array (15 downto 0) of std_ulogic_vector(data_width_c-1 downto 0);
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type reg_file_emb_t is array (15 downto 0) of std_ulogic_vector(data_width_c-1 downto 0);
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signal reg_file : reg_file_t;
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signal reg_file : reg_file_t;
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signal reg_file_emb : reg_file_emb_t;
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signal reg_file_emb : reg_file_emb_t;
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signal rf_write_data : std_ulogic_vector(data_width_c-1 downto 0); -- actual write-back data
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signal rf_write_data : std_ulogic_vector(data_width_c-1 downto 0); -- actual write-back data
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signal valid_wr : std_ulogic; -- writing not to r0
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signal rs1_read : std_ulogic_vector(data_width_c-1 downto 0); -- internal operand rs1
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signal rs1_read : std_ulogic_vector(data_width_c-1 downto 0); -- internal operand rs1
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signal rs2_read : std_ulogic_vector(data_width_c-1 downto 0); -- internal operand rs2
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signal rs2_read : std_ulogic_vector(data_width_c-1 downto 0); -- internal operand rs2
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-- reading from r0? --
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-- reading from r0? --
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signal rs1_clear, rs2_clear : std_ulogic;
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signal rs1_clear, rs2_clear : std_ulogic;
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when "10" => rf_write_data <= pc_i;
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when "10" => rf_write_data <= pc_i;
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when others => rf_write_data <= csr_i;
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when others => rf_write_data <= csr_i;
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end case;
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end case;
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end process input_mux;
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end process input_mux;
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-- only write if destination is not x0 (pretty irrelevant, but might save some power) --
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valid_wr <= or_all_f(ctrl_i(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c)) when (CPU_EXTENSION_RISCV_E = false) else
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or_all_f(ctrl_i(ctrl_rf_rd_adr3_c downto ctrl_rf_rd_adr0_c));
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-- Register file read/write access --------------------------------------------------------
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-- Register file read/write access --------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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rf_access: process(clk_i)
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rf_access: process(clk_i)
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begin
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begin
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end if;
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end if;
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if (ctrl_i(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c) = "00000") then
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if (ctrl_i(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c) = "00000") then
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rs2_clear <= '1';
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rs2_clear <= '1';
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end if;
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end if;
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-- write --
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-- write --
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if (ctrl_i(ctrl_rf_wb_en_c) = '1') then -- valid write-back
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if (ctrl_i(ctrl_rf_wb_en_c) = '1') and (valid_wr = '1') then -- valid write-back
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reg_file(to_integer(unsigned(ctrl_i(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c)))) <= rf_write_data;
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reg_file(to_integer(unsigned(ctrl_i(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c)))) <= rf_write_data;
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end if;
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end if;
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-- read --
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-- read --
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rs1_read <= reg_file(to_integer(unsigned(ctrl_i(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c))));
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rs1_read <= reg_file(to_integer(unsigned(ctrl_i(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c))));
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rs2_read <= reg_file(to_integer(unsigned(ctrl_i(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c))));
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rs2_read <= reg_file(to_integer(unsigned(ctrl_i(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c))));
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end if;
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end if;
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if (ctrl_i(ctrl_rf_rs2_adr3_c downto ctrl_rf_rs2_adr0_c) = "0000") then
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if (ctrl_i(ctrl_rf_rs2_adr3_c downto ctrl_rf_rs2_adr0_c) = "0000") then
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rs2_clear <= '1';
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rs2_clear <= '1';
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end if;
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end if;
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-- write --
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-- write --
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if (ctrl_i(ctrl_rf_wb_en_c) = '1') then -- valid write-back
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if (ctrl_i(ctrl_rf_wb_en_c) = '1') and (valid_wr = '1') then -- valid write-back
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reg_file_emb(to_integer(unsigned(ctrl_i(ctrl_rf_rd_adr3_c downto ctrl_rf_rd_adr0_c)))) <= rf_write_data;
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reg_file_emb(to_integer(unsigned(ctrl_i(ctrl_rf_rd_adr3_c downto ctrl_rf_rd_adr0_c)))) <= rf_write_data;
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end if;
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end if;
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-- read --
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-- read --
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rs1_read <= reg_file_emb(to_integer(unsigned(ctrl_i(ctrl_rf_rs1_adr3_c downto ctrl_rf_rs1_adr0_c))));
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rs1_read <= reg_file_emb(to_integer(unsigned(ctrl_i(ctrl_rf_rs1_adr3_c downto ctrl_rf_rs1_adr0_c))));
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rs2_read <= reg_file_emb(to_integer(unsigned(ctrl_i(ctrl_rf_rs2_adr3_c downto ctrl_rf_rs2_adr0_c))));
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rs2_read <= reg_file_emb(to_integer(unsigned(ctrl_i(ctrl_rf_rs2_adr3_c downto ctrl_rf_rs2_adr0_c))));
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