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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_cpu_regfile.vhd] - Diff between revs 24 and 25

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-- #################################################################################################
-- #################################################################################################
-- # << NEORV32 - CPU Register File >>                                                             #
-- # << NEORV32 - CPU Register File >>                                                             #
-- # ********************************************************************************************* #
-- # ********************************************************************************************* #
-- # General purpose data registers. 32 entries for normal mode, 16 entries for embedded mode when #
-- # General purpose data registers. 32 entries for normal mode, 16 entries for embedded mode when #
-- # RISC-V M extension is enabled. x0 output is allways set to zero.                              #
-- # RISC-V "E" extension is enabled. Register zero (r0/x0) is a normal physical registers, that   #
 
-- # has to be initialized to zero by the CPU control system. For normal operations, x0 cannot be  #
 
-- # written.                                                                                      #
-- # ********************************************************************************************* #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License                                                                          #
-- # BSD 3-Clause License                                                                          #
-- #                                                                                               #
-- #                                                                                               #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved.                                     #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved.                                     #
-- #                                                                                               #
-- #                                                                                               #
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  type   reg_file_emb_t is array (15 downto 0) of std_ulogic_vector(data_width_c-1 downto 0);
  type   reg_file_emb_t is array (15 downto 0) of std_ulogic_vector(data_width_c-1 downto 0);
  signal reg_file      : reg_file_t;
  signal reg_file      : reg_file_t;
  signal reg_file_emb  : reg_file_emb_t;
  signal reg_file_emb  : reg_file_emb_t;
  signal rf_write_data : std_ulogic_vector(data_width_c-1 downto 0); -- actual write-back data
  signal rf_write_data : std_ulogic_vector(data_width_c-1 downto 0); -- actual write-back data
  signal valid_wr      : std_ulogic; -- writing not to r0
  signal valid_wr      : std_ulogic; -- writing not to r0
  signal rs1_read      : std_ulogic_vector(data_width_c-1 downto 0); -- internal operand rs1
 
  signal rs2_read      : std_ulogic_vector(data_width_c-1 downto 0); -- internal operand rs2
 
 
 
  -- reading from r0? --
 
  signal rs1_clear, rs2_clear : std_ulogic;
 
 
 
 
 
  -- attributes - these are *NOT mandatory*; just for footprint / timing optimization --
  -- attributes - these are *NOT mandatory*; just for footprint / timing optimization --
  -- -------------------------------------------------------------------------------- --
  -- -------------------------------------------------------------------------------- --
 
 
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      when "10"   => rf_write_data <= pc_i;
      when "10"   => rf_write_data <= pc_i;
      when others => rf_write_data <= csr_i;
      when others => rf_write_data <= csr_i;
    end case;
    end case;
  end process input_mux;
  end process input_mux;
 
 
  -- only write if destination is not x0 (pretty irrelevant, but might save some power) --
  -- only write if destination is not x0; except we are forcing a r0 write access --
  valid_wr <= or_all_f(ctrl_i(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c)) when (CPU_EXTENSION_RISCV_E = false) else
  valid_wr <= or_all_f(ctrl_i(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c)) or ctrl_i(ctrl_rf_r0_we_c) when (CPU_EXTENSION_RISCV_E = false) else
              or_all_f(ctrl_i(ctrl_rf_rd_adr3_c downto ctrl_rf_rd_adr0_c));
              or_all_f(ctrl_i(ctrl_rf_rd_adr3_c downto ctrl_rf_rd_adr0_c)) or ctrl_i(ctrl_rf_r0_we_c);
 
 
 
 
  -- Register file read/write access --------------------------------------------------------
  -- Register file read/write access --------------------------------------------------------
  -- -------------------------------------------------------------------------------------------
  -- -------------------------------------------------------------------------------------------
  rf_access: process(clk_i)
  rf_access: process(clk_i)
  begin
  begin
    if rising_edge(clk_i) then -- sync read and write
    if rising_edge(clk_i) then -- sync read and write
      if (CPU_EXTENSION_RISCV_E = false) then -- normal register file with 32 entries
      if (CPU_EXTENSION_RISCV_E = false) then -- normal register file with 32 entries
        -- check if reading from r0 --
 
        rs1_clear <= '0';
 
        rs2_clear <= '0';
 
        if (ctrl_i(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c) = "00000") then
 
          rs1_clear <= '1';
 
        end if;
 
        if (ctrl_i(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c) = "00000") then
 
          rs2_clear <= '1';
 
        end if;
 
        -- write --
        -- write --
        if (ctrl_i(ctrl_rf_wb_en_c) = '1') and (valid_wr = '1') then -- valid write-back
        if (ctrl_i(ctrl_rf_wb_en_c) = '1') and ((valid_wr = '1') or (rf_r0_is_reg_c = false)) then -- valid write-back
          reg_file(to_integer(unsigned(ctrl_i(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c)))) <= rf_write_data;
          reg_file(to_integer(unsigned(ctrl_i(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c)))) <= rf_write_data;
        end if;
        end if;
        -- read --
        -- read --
        rs1_read <= reg_file(to_integer(unsigned(ctrl_i(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c))));
        rs1_o <= reg_file(to_integer(unsigned(ctrl_i(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c))));
        rs2_read <= reg_file(to_integer(unsigned(ctrl_i(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c))));
        rs2_o <= reg_file(to_integer(unsigned(ctrl_i(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c))));
 
 
      else -- embedded register file with 16 entries
      else -- embedded register file with 16 entries
        -- check if reading from r0 --
 
        rs1_clear <= '0';
 
        rs2_clear <= '0';
 
        if (ctrl_i(ctrl_rf_rs1_adr3_c downto ctrl_rf_rs1_adr0_c) = "0000") then
 
          rs1_clear <= '1';
 
        end if;
 
        if (ctrl_i(ctrl_rf_rs2_adr3_c downto ctrl_rf_rs2_adr0_c) = "0000") then
 
          rs2_clear <= '1';
 
        end if;
 
        -- write --
        -- write --
        if (ctrl_i(ctrl_rf_wb_en_c) = '1') and (valid_wr = '1') then -- valid write-back
        if (ctrl_i(ctrl_rf_wb_en_c) = '1') and ((valid_wr = '1') or (rf_r0_is_reg_c = false)) then -- valid write-back
          reg_file_emb(to_integer(unsigned(ctrl_i(ctrl_rf_rd_adr3_c downto ctrl_rf_rd_adr0_c)))) <= rf_write_data;
          reg_file_emb(to_integer(unsigned(ctrl_i(ctrl_rf_rd_adr3_c downto ctrl_rf_rd_adr0_c)))) <= rf_write_data;
        end if;
        end if;
        -- read --
        -- read --
        rs1_read <= reg_file_emb(to_integer(unsigned(ctrl_i(ctrl_rf_rs1_adr3_c downto ctrl_rf_rs1_adr0_c))));
        rs1_o <= reg_file_emb(to_integer(unsigned(ctrl_i(ctrl_rf_rs1_adr3_c downto ctrl_rf_rs1_adr0_c))));
        rs2_read <= reg_file_emb(to_integer(unsigned(ctrl_i(ctrl_rf_rs2_adr3_c downto ctrl_rf_rs2_adr0_c))));
        rs2_o <= reg_file_emb(to_integer(unsigned(ctrl_i(ctrl_rf_rs2_adr3_c downto ctrl_rf_rs2_adr0_c))));
      end if;
      end if;
    end if;
    end if;
  end process rf_access;
  end process rf_access;
 
 
 
 
  -- Check if reading from x0 ---------------------------------------------------------------
 
  -- -------------------------------------------------------------------------------------------
 
  rs1_o <= (others => '0') when ((rs1_clear or ctrl_i(ctrl_rf_clear_rs1_c)) = '1') else rs1_read;
 
  rs2_o <= (others => '0') when (rs2_clear = '1') else rs2_read;
 
 
 
 
 
end neorv32_cpu_regfile_rtl;
end neorv32_cpu_regfile_rtl;
 
 
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