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-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - CPU Data Register File >> #
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-- # << NEORV32 - CPU Data Register File >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # General purpose data register file. 32 entries for normal mode (I), 16 entries for embedded #
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-- # General purpose data register file. 32 entries for normal mode (I), 16 entries for embedded #
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-- # mode (E) when RISC-V "E" extension is enabled. Register zero (r0) is a normal physical #
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-- # mode (E) when RISC-V "E" extension is enabled. Register zero (r0) is a "normal" physical reg #
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-- # registers, that has to be initialized to zero by the CPU control system. For normal #
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-- # that has to be initialized to zero by the CPU control system. For normal operations r0 cannot #
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-- # operations r0 cannot be written. The register file uses synchronous reads. Hence it can be #
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-- # be written. The register file uses synchronous reads so it can be mapped to FPGA block RAM. #
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-- # mapped to FPGA block RAM. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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-- data input --
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-- data input --
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mem_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
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mem_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
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alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
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alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
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csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
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csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
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pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- current pc
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-- data output --
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-- data output --
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rs1_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 1
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rs1_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 1
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rs2_o : out std_ulogic_vector(data_width_c-1 downto 0) -- operand 2
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rs2_o : out std_ulogic_vector(data_width_c-1 downto 0) -- operand 2
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);
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);
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end neorv32_cpu_regfile;
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end neorv32_cpu_regfile;
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-- register file --
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-- register file --
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type reg_file_t is array (31 downto 0) of std_ulogic_vector(data_width_c-1 downto 0);
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type reg_file_t is array (31 downto 0) of std_ulogic_vector(data_width_c-1 downto 0);
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type reg_file_emb_t is array (15 downto 0) of std_ulogic_vector(data_width_c-1 downto 0);
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type reg_file_emb_t is array (15 downto 0) of std_ulogic_vector(data_width_c-1 downto 0);
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signal reg_file : reg_file_t;
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signal reg_file : reg_file_t;
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signal reg_file_emb : reg_file_emb_t;
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signal reg_file_emb : reg_file_emb_t;
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signal rf_mux_data : std_ulogic_vector(data_width_c-1 downto 0);
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signal rf_write_data : std_ulogic_vector(data_width_c-1 downto 0); -- actual write-back data
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signal rf_write_data : std_ulogic_vector(data_width_c-1 downto 0); -- actual write-back data
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signal rd_is_r0 : std_ulogic; -- writing to r0?
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signal rd_is_r0 : std_ulogic; -- writing to r0?
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signal rf_we : std_ulogic;
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signal rf_we : std_ulogic;
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signal dst_addr : std_ulogic_vector(4 downto 0); -- destination address
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signal dst_addr : std_ulogic_vector(4 downto 0); -- destination address
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begin
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begin
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-- Input mux ------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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input_mux: process(ctrl_i, mem_i, alu_i, pc_i, csr_i)
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begin
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case ctrl_i(ctrl_rf_in_mux_msb_c downto ctrl_rf_in_mux_lsb_c) is
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when "00" => rf_write_data <= alu_i;
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when "01" => rf_write_data <= mem_i;
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when "10" => rf_write_data <= pc_i;
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when others => rf_write_data <= csr_i;
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end case;
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end process input_mux;
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-- check if we are writing to x0 --
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rd_is_r0 <= not or_all_f(ctrl_i(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c)) when (CPU_EXTENSION_RISCV_E = false) else
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not or_all_f(ctrl_i(ctrl_rf_rd_adr3_c downto ctrl_rf_rd_adr0_c));
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-- valid RF write access --
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rf_we <= (ctrl_i(ctrl_rf_wb_en_c) and (not rd_is_r0)) or ctrl_i(ctrl_rf_r0_we_c);
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-- destination address --
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dst_addr <= ctrl_i(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c) when (ctrl_i(ctrl_rf_r0_we_c) = '0') else (others => '0'); -- force dst=r0?
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-- Register file read/write access --------------------------------------------------------
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-- Register file read/write access --------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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rf_access: process(clk_i)
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rf_access: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then -- sync read and write
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if rising_edge(clk_i) then -- sync read and write
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if (CPU_EXTENSION_RISCV_E = false) then -- normal register file with 32 entries
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if (CPU_EXTENSION_RISCV_E = false) then -- normal register file with 32 entries
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if (rf_we = '1') then
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if (rf_we = '1') then
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reg_file(to_integer(unsigned(dst_addr(4 downto 0)))) <= rf_write_data;
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reg_file(to_integer(unsigned(dst_addr(4 downto 0)))) <= rf_write_data;
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else -- read
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else
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rs1_o <= reg_file(to_integer(unsigned(ctrl_i(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c))));
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rs1_o <= reg_file(to_integer(unsigned(ctrl_i(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c))));
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rs2_o <= reg_file(to_integer(unsigned(ctrl_i(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c))));
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rs2_o <= reg_file(to_integer(unsigned(ctrl_i(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c))));
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end if;
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end if;
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else -- embedded register file with 16 entries
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else -- embedded register file with 16 entries
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if (rf_we = '1') then
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if (rf_we = '1') then
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reg_file_emb(to_integer(unsigned(dst_addr(3 downto 0)))) <= rf_write_data;
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reg_file_emb(to_integer(unsigned(dst_addr(3 downto 0)))) <= rf_write_data;
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else -- read
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else
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rs1_o <= reg_file_emb(to_integer(unsigned(ctrl_i(ctrl_rf_rs1_adr3_c downto ctrl_rf_rs1_adr0_c))));
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rs1_o <= reg_file_emb(to_integer(unsigned(ctrl_i(ctrl_rf_rs1_adr3_c downto ctrl_rf_rs1_adr0_c))));
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rs2_o <= reg_file_emb(to_integer(unsigned(ctrl_i(ctrl_rf_rs2_adr3_c downto ctrl_rf_rs2_adr0_c))));
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rs2_o <= reg_file_emb(to_integer(unsigned(ctrl_i(ctrl_rf_rs2_adr3_c downto ctrl_rf_rs2_adr0_c))));
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process rf_access;
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end process rf_access;
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-- data input mux --
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rf_write_data <= alu_i when (ctrl_i(ctrl_rf_in_mux_msb_c) = '0') else rf_mux_data;
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rf_mux_data <= mem_i when (ctrl_i(ctrl_rf_in_mux_lsb_c) = '0') else csr_i;
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-- check if we are writing to x0 --
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rd_is_r0 <= not or_all_f(ctrl_i(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c)) when (CPU_EXTENSION_RISCV_E = false) else
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not or_all_f(ctrl_i(ctrl_rf_rd_adr3_c downto ctrl_rf_rd_adr0_c));
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-- valid RF write access --
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rf_we <= (ctrl_i(ctrl_rf_wb_en_c) and (not rd_is_r0)) or ctrl_i(ctrl_rf_r0_we_c);
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-- destination address --
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dst_addr <= ctrl_i(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c) when (ctrl_i(ctrl_rf_r0_we_c) = '0') else (others => '0'); -- force dst=r0?
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end neorv32_cpu_regfile_rtl;
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end neorv32_cpu_regfile_rtl;
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No newline at end of file
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No newline at end of file
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