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-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - CPU Data Register File >> #
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-- # << NEORV32 - CPU General Purpose Data Register File >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # General purpose data register file. 32 entries for normal mode (I), 16 entries for embedded #
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-- # General purpose data register file. 32 entries (= 1024 bit) for normal mode (RV32I), #
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-- # mode (E) when RISC-V "E" extension is enabled. Register zero (r0) is a "normal" physical reg #
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-- # 16 entries (= 512 bit) for embedded mode (RV32E) when RISC-V "E" extension is enabled. #
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-- # that has to be initialized to zero by the CPU control system. For normal operations r0 cannot #
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-- # #
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-- # be written. The register file uses synchronous reads so it can be mapped to FPGA block RAM. #
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-- # Register zero (r0/x0) is a "normal" physical reg that has to be initialized to zero by the #
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-- # CPU control system. For normal operations register zero cannot be written. #
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-- # #
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-- # The register file uses synchronous read accesses and a *single* (multiplexed) address port #
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-- # for writing and reading rs1 and a single read-only port for rs2. Therefore, the whole #
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-- # register file can be mapped to a single true dual-port block RAM. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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signal rf_mux_data : std_ulogic_vector(data_width_c-1 downto 0);
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signal rf_mux_data : std_ulogic_vector(data_width_c-1 downto 0);
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signal rf_write_data : std_ulogic_vector(data_width_c-1 downto 0); -- actual write-back data
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signal rf_write_data : std_ulogic_vector(data_width_c-1 downto 0); -- actual write-back data
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signal rd_is_r0 : std_ulogic; -- writing to r0?
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signal rd_is_r0 : std_ulogic; -- writing to r0?
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signal rf_we : std_ulogic;
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signal rf_we : std_ulogic;
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signal dst_addr : std_ulogic_vector(4 downto 0); -- destination address
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signal dst_addr : std_ulogic_vector(4 downto 0); -- destination address
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signal opa_addr : std_ulogic_vector(4 downto 0); -- rs1/dst address
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signal opb_addr : std_ulogic_vector(4 downto 0); -- rs2 address
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begin
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begin
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-- Register file read/write access --------------------------------------------------------
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-- Data Input Mux -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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rf_mux_data <= mem_i when (ctrl_i(ctrl_rf_in_mux_lsb_c) = '0') else csr_i;
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rf_write_data <= alu_i when (ctrl_i(ctrl_rf_in_mux_msb_c) = '0') else rf_mux_data;
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-- Register File Access -------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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rf_access: process(clk_i)
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rf_access: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then -- sync read and write
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if rising_edge(clk_i) then -- sync read and write
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if (CPU_EXTENSION_RISCV_E = false) then -- normal register file with 32 entries
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if (CPU_EXTENSION_RISCV_E = false) then -- normal register file with 32 entries
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if (rf_we = '1') then
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if (rf_we = '1') then
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reg_file(to_integer(unsigned(dst_addr(4 downto 0)))) <= rf_write_data;
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reg_file(to_integer(unsigned(opa_addr(4 downto 0)))) <= rf_write_data;
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else
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rs1_o <= reg_file(to_integer(unsigned(ctrl_i(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c))));
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rs2_o <= reg_file(to_integer(unsigned(ctrl_i(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c))));
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end if;
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end if;
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rs1_o <= reg_file(to_integer(unsigned(opa_addr(4 downto 0))));
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rs2_o <= reg_file(to_integer(unsigned(opb_addr(4 downto 0))));
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else -- embedded register file with 16 entries
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else -- embedded register file with 16 entries
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if (rf_we = '1') then
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if (rf_we = '1') then
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reg_file_emb(to_integer(unsigned(dst_addr(3 downto 0)))) <= rf_write_data;
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reg_file_emb(to_integer(unsigned(opa_addr(3 downto 0)))) <= rf_write_data;
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else
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rs1_o <= reg_file_emb(to_integer(unsigned(ctrl_i(ctrl_rf_rs1_adr3_c downto ctrl_rf_rs1_adr0_c))));
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rs2_o <= reg_file_emb(to_integer(unsigned(ctrl_i(ctrl_rf_rs2_adr3_c downto ctrl_rf_rs2_adr0_c))));
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end if;
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end if;
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rs1_o <= reg_file_emb(to_integer(unsigned(opa_addr(3 downto 0))));
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rs2_o <= reg_file_emb(to_integer(unsigned(opb_addr(3 downto 0))));
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end if;
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end if;
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end if;
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end if;
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end process rf_access;
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end process rf_access;
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-- data input mux --
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rf_write_data <= alu_i when (ctrl_i(ctrl_rf_in_mux_msb_c) = '0') else rf_mux_data;
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rf_mux_data <= mem_i when (ctrl_i(ctrl_rf_in_mux_lsb_c) = '0') else csr_i;
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-- check if we are writing to x0 --
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-- check if we are writing to x0 --
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rd_is_r0 <= not or_all_f(ctrl_i(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c)) when (CPU_EXTENSION_RISCV_E = false) else
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rd_is_r0 <= not or_all_f(ctrl_i(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c)) when (CPU_EXTENSION_RISCV_E = false) else
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not or_all_f(ctrl_i(ctrl_rf_rd_adr3_c downto ctrl_rf_rd_adr0_c));
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not or_all_f(ctrl_i(ctrl_rf_rd_adr3_c downto ctrl_rf_rd_adr0_c));
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-- valid RF write access --
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-- valid RF write access? --
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rf_we <= (ctrl_i(ctrl_rf_wb_en_c) and (not rd_is_r0)) or ctrl_i(ctrl_rf_r0_we_c);
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rf_we <= (ctrl_i(ctrl_rf_wb_en_c) and (not rd_is_r0)) or ctrl_i(ctrl_rf_r0_we_c);
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-- destination address --
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-- destination address --
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dst_addr <= ctrl_i(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c) when (ctrl_i(ctrl_rf_r0_we_c) = '0') else (others => '0'); -- force dst=r0?
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dst_addr <= ctrl_i(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c) when (ctrl_i(ctrl_rf_r0_we_c) = '0') else (others => '0'); -- force dst=r0?
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-- access addresses --
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opa_addr <= dst_addr when (rf_we = '1') else ctrl_i(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c); -- rd/rs1
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opb_addr <= ctrl_i(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c); -- rs2
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end neorv32_cpu_regfile_rtl;
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end neorv32_cpu_regfile_rtl;
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