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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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-- data input --
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-- data input --
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mem_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
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mem_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
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alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
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alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
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csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
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-- data output --
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-- data output --
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rs1_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 1
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rs1_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 1
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rs2_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 2
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rs2_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 2
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cmp_o : out std_ulogic_vector(1 downto 0) -- comparator status
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cmp_o : out std_ulogic_vector(1 downto 0) -- comparator status
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);
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);
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-- register file --
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-- register file --
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type reg_file_t is array (31 downto 0) of std_ulogic_vector(data_width_c-1 downto 0);
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type reg_file_t is array (31 downto 0) of std_ulogic_vector(data_width_c-1 downto 0);
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type reg_file_emb_t is array (15 downto 0) of std_ulogic_vector(data_width_c-1 downto 0);
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type reg_file_emb_t is array (15 downto 0) of std_ulogic_vector(data_width_c-1 downto 0);
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signal reg_file : reg_file_t;
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signal reg_file : reg_file_t;
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signal reg_file_emb : reg_file_emb_t;
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signal reg_file_emb : reg_file_emb_t;
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signal rf_mux_data : std_ulogic_vector(data_width_c-1 downto 0);
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signal rf_wdata : std_ulogic_vector(data_width_c-1 downto 0); -- actual write-back data
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signal rf_write_data : std_ulogic_vector(data_width_c-1 downto 0); -- actual write-back data
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signal rd_is_r0 : std_ulogic; -- writing to r0?
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signal rd_is_r0 : std_ulogic; -- writing to r0?
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signal rf_we : std_ulogic;
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signal rf_we : std_ulogic;
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signal dst_addr : std_ulogic_vector(4 downto 0); -- destination address
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signal dst_addr : std_ulogic_vector(4 downto 0); -- destination address
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signal opa_addr : std_ulogic_vector(4 downto 0); -- rs1/dst address
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signal opa_addr : std_ulogic_vector(4 downto 0); -- rs1/dst address
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signal opb_addr : std_ulogic_vector(4 downto 0); -- rs2 address
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signal opb_addr : std_ulogic_vector(4 downto 0); -- rs2 address
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begin
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begin
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-- Data Input Mux -------------------------------------------------------------------------
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-- Data Input Mux -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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rf_mux_data <= mem_i when (ctrl_i(ctrl_rf_in_mux_lsb_c) = '0') else csr_i;
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rf_wdata <= alu_i when (ctrl_i(ctrl_rf_in_mux_c) = '0') else mem_i;
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rf_write_data <= alu_i when (ctrl_i(ctrl_rf_in_mux_msb_c) = '0') else rf_mux_data;
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-- Register File Access -------------------------------------------------------------------
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-- Register File Access -------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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rf_access: process(clk_i)
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rf_access: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then -- sync read and write
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if rising_edge(clk_i) then -- sync read and write
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if (CPU_EXTENSION_RISCV_E = false) then -- normal register file with 32 entries
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if (CPU_EXTENSION_RISCV_E = false) then -- normal register file with 32 entries
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if (rf_we = '1') then
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if (rf_we = '1') then
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reg_file(to_integer(unsigned(opa_addr(4 downto 0)))) <= rf_write_data;
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reg_file(to_integer(unsigned(opa_addr(4 downto 0)))) <= rf_wdata;
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end if;
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end if;
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rs1 <= reg_file(to_integer(unsigned(opa_addr(4 downto 0))));
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rs1 <= reg_file(to_integer(unsigned(opa_addr(4 downto 0))));
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rs2 <= reg_file(to_integer(unsigned(opb_addr(4 downto 0))));
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rs2 <= reg_file(to_integer(unsigned(opb_addr(4 downto 0))));
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else -- embedded register file with 16 entries
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else -- embedded register file with 16 entries
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if (rf_we = '1') then
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if (rf_we = '1') then
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reg_file_emb(to_integer(unsigned(opa_addr(3 downto 0)))) <= rf_write_data;
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reg_file_emb(to_integer(unsigned(opa_addr(3 downto 0)))) <= rf_wdata;
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end if;
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end if;
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rs1 <= reg_file_emb(to_integer(unsigned(opa_addr(3 downto 0))));
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rs1 <= reg_file_emb(to_integer(unsigned(opa_addr(3 downto 0))));
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rs2 <= reg_file_emb(to_integer(unsigned(opb_addr(3 downto 0))));
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rs2 <= reg_file_emb(to_integer(unsigned(opb_addr(3 downto 0))));
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end if;
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end if;
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end if;
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end if;
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