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library neorv32;
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library neorv32;
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use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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entity neorv32_cpu_regfile is
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entity neorv32_cpu_regfile is
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generic (
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generic (
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CPU_EXTENSION_RISCV_E : boolean := false -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E : boolean -- implement embedded RF extension?
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);
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);
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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type reg_file_emb_t is array (15 downto 0) of std_ulogic_vector(data_width_c-1 downto 0);
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type reg_file_emb_t is array (15 downto 0) of std_ulogic_vector(data_width_c-1 downto 0);
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signal reg_file : reg_file_t;
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signal reg_file : reg_file_t;
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signal reg_file_emb : reg_file_emb_t;
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signal reg_file_emb : reg_file_emb_t;
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signal rf_wdata : std_ulogic_vector(data_width_c-1 downto 0); -- actual write-back data
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signal rf_wdata : std_ulogic_vector(data_width_c-1 downto 0); -- actual write-back data
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signal rd_is_r0 : std_ulogic; -- writing to r0?
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signal rd_is_r0 : std_ulogic; -- writing to r0?
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signal rf_we : std_ulogic;
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signal dst_addr : std_ulogic_vector(4 downto 0); -- destination address
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signal dst_addr : std_ulogic_vector(4 downto 0); -- destination address
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signal opa_addr : std_ulogic_vector(4 downto 0); -- rs1/dst address
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signal opa_addr : std_ulogic_vector(4 downto 0); -- rs1/dst address
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signal opb_addr : std_ulogic_vector(4 downto 0); -- rs2 address
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signal opb_addr : std_ulogic_vector(4 downto 0); -- rs2 address
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signal rs1, rs2 : std_ulogic_vector(data_width_c-1 downto 0);
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signal rs1, rs2 : std_ulogic_vector(data_width_c-1 downto 0); -- read data
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-- comparator --
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-- comparator --
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signal cmp_opx : std_ulogic_vector(data_width_c downto 0);
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signal cmp_opx : std_ulogic_vector(data_width_c downto 0);
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signal cmp_opy : std_ulogic_vector(data_width_c downto 0);
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signal cmp_opy : std_ulogic_vector(data_width_c downto 0);
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begin
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begin
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-- Data Input Mux -------------------------------------------------------------------------
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-- Data Input Mux -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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rf_wdata <= alu_i when (ctrl_i(ctrl_rf_in_mux_c) = '0') else mem_i;
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input_mux: process(rd_is_r0, ctrl_i, alu_i, mem_i)
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begin
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if (rd_is_r0 = '1') then -- write zero if accessing x0 to "emulate" it is hardwired to zero
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rf_wdata <= (others => '0');
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else
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if (ctrl_i(ctrl_rf_in_mux_c) = '0') then
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rf_wdata <= alu_i;
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else
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rf_wdata <= mem_i;
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end if;
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end if;
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end process input_mux;
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-- check if we are writing to x0 --
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rd_is_r0 <= (not or_reduce_f(dst_addr(4 downto 0))) when (CPU_EXTENSION_RISCV_E = false) else (not or_reduce_f(dst_addr(3 downto 0)));
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-- Register File Access -------------------------------------------------------------------
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-- Register File Access -------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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rf_access: process(clk_i)
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rf_access: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then -- sync read and write
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if rising_edge(clk_i) then -- sync read and write
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if (CPU_EXTENSION_RISCV_E = false) then -- normal register file with 32 entries
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if (CPU_EXTENSION_RISCV_E = false) then -- normal register file with 32 entries
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if (rf_we = '1') then
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if (ctrl_i(ctrl_rf_wb_en_c) = '1') then
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reg_file(to_integer(unsigned(opa_addr(4 downto 0)))) <= rf_wdata;
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reg_file(to_integer(unsigned(opa_addr(4 downto 0)))) <= rf_wdata;
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end if;
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end if;
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rs1 <= reg_file(to_integer(unsigned(opa_addr(4 downto 0))));
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rs1 <= reg_file(to_integer(unsigned(opa_addr(4 downto 0))));
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rs2 <= reg_file(to_integer(unsigned(opb_addr(4 downto 0))));
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rs2 <= reg_file(to_integer(unsigned(opb_addr(4 downto 0))));
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else -- embedded register file with 16 entries
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else -- embedded register file with 16 entries
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if (rf_we = '1') then
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if (ctrl_i(ctrl_rf_wb_en_c) = '1') then
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reg_file_emb(to_integer(unsigned(opa_addr(3 downto 0)))) <= rf_wdata;
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reg_file_emb(to_integer(unsigned(opa_addr(3 downto 0)))) <= rf_wdata;
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end if;
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end if;
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rs1 <= reg_file_emb(to_integer(unsigned(opa_addr(3 downto 0))));
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rs1 <= reg_file_emb(to_integer(unsigned(opa_addr(3 downto 0))));
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rs2 <= reg_file_emb(to_integer(unsigned(opb_addr(3 downto 0))));
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rs2 <= reg_file_emb(to_integer(unsigned(opb_addr(3 downto 0))));
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end if;
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end if;
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end if;
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end if;
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end process rf_access;
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end process rf_access;
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-- check if we are writing to x0 --
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rd_is_r0 <= not or_reduce_f(ctrl_i(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c)) when (CPU_EXTENSION_RISCV_E = false) else
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not or_reduce_f(ctrl_i(ctrl_rf_rd_adr3_c downto ctrl_rf_rd_adr0_c));
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-- valid RF write access? --
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rf_we <= (ctrl_i(ctrl_rf_wb_en_c) and (not rd_is_r0)) or ctrl_i(ctrl_rf_r0_we_c);
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-- access addresses --
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-- access addresses --
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dst_addr <= ctrl_i(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c) when (ctrl_i(ctrl_rf_r0_we_c) = '0') else (others => '0'); -- force dst=r0?
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dst_addr <= ctrl_i(ctrl_rf_rd_adr4_c downto ctrl_rf_rd_adr0_c);
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opa_addr <= dst_addr when (rf_we = '1') else ctrl_i(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c); -- rd/rs1
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opa_addr <= dst_addr when (ctrl_i(ctrl_rf_wb_en_c) = '1') else ctrl_i(ctrl_rf_rs1_adr4_c downto ctrl_rf_rs1_adr0_c); -- rd/rs1
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opb_addr <= ctrl_i(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c); -- rs2
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opb_addr <= ctrl_i(ctrl_rf_rs2_adr4_c downto ctrl_rf_rs2_adr0_c); -- rs2
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-- data output --
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-- data output --
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rs1_o <= rs1;
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rs1_o <= rs1;
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rs2_o <= rs2;
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rs2_o <= rs2;
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