| Line 425... |
Line 425... |
dm_reg.clr_acc_err <= '0';
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dm_reg.clr_acc_err <= '0';
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dm_reg.autoexec_wr <= '0';
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dm_reg.autoexec_wr <= '0';
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elsif rising_edge(clk_i) then
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elsif rising_edge(clk_i) then
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|
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-- default --
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-- default --
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dm_reg.halt_req <= '0';
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dm_reg.resume_req <= '0';
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dm_reg.resume_req <= '0';
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dm_reg.reset_ack <= '0';
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dm_reg.reset_ack <= '0';
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dm_reg.wr_acc_err <= '0';
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dm_reg.wr_acc_err <= '0';
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dm_reg.clr_acc_err <= '0';
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dm_reg.clr_acc_err <= '0';
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dm_reg.autoexec_wr <= '0';
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dm_reg.autoexec_wr <= '0';
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| Line 437... |
Line 436... |
-- DMI access --
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-- DMI access --
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if (dmi_req_valid_i = '1') and (dmi_req_op_i = '1') then -- valid DMI write request
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if (dmi_req_valid_i = '1') and (dmi_req_op_i = '1') then -- valid DMI write request
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|
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-- debug module control --
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-- debug module control --
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if (dmi_req_addr_i = addr_dmcontrol_c) then
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if (dmi_req_addr_i = addr_dmcontrol_c) then
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dm_reg.halt_req <= dmi_req_data_i(31); -- haltreq (-/w): write 1 to request halt
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dm_reg.halt_req <= dmi_req_data_i(31); -- haltreq (-/w): write 1 to request halt; has to be cleared again by debugger
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dm_reg.resume_req <= dmi_req_data_i(30); -- resumereq (-/w1): write 1 to request resume
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dm_reg.resume_req <= dmi_req_data_i(30); -- resumereq (-/w1): write 1 to request resume
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dm_reg.reset_ack <= dmi_req_data_i(28); -- ackhavereset (-/w1)
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dm_reg.reset_ack <= dmi_req_data_i(28); -- ackhavereset (-/w1)
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dm_reg.dmcontrol_ndmreset <= dmi_req_data_i(01); -- ndmreset (r/w): soc reset
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dm_reg.dmcontrol_ndmreset <= dmi_req_data_i(01); -- ndmreset (r/w): soc reset
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dm_reg.dmcontrol_dmactive <= dmi_req_data_i(00); -- dmactive (r/w): DM reset
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dm_reg.dmcontrol_dmactive <= dmi_req_data_i(00); -- dmactive (r/w): DM reset
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end if;
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end if;
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