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-- # * data buffer #
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-- # * data buffer #
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-- # * control and status register #
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-- # * control and status register #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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dmi_resp_valid_o : out std_ulogic; -- response valid when set
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dmi_resp_valid_o : out std_ulogic; -- response valid when set
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dmi_resp_ready_i : in std_ulogic; -- ready to receive respond
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dmi_resp_ready_i : in std_ulogic; -- ready to receive respond
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dmi_resp_data_o : out std_ulogic_vector(31 downto 0);
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dmi_resp_data_o : out std_ulogic_vector(31 downto 0);
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dmi_resp_err_o : out std_ulogic; -- 0=ok, 1=error
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dmi_resp_err_o : out std_ulogic; -- 0=ok, 1=error
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-- CPU bus access --
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-- CPU bus access --
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cpu_debug_i : in std_ulogic; -- CPU is in debug mode
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cpu_addr_i : in std_ulogic_vector(31 downto 0); -- address
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cpu_addr_i : in std_ulogic_vector(31 downto 0); -- address
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cpu_rden_i : in std_ulogic; -- read enable
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cpu_rden_i : in std_ulogic; -- read enable
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cpu_wren_i : in std_ulogic; -- write enable
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cpu_wren_i : in std_ulogic; -- write enable
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cpu_data_i : in std_ulogic_vector(31 downto 0); -- data in
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cpu_data_i : in std_ulogic_vector(31 downto 0); -- data in
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cpu_data_o : out std_ulogic_vector(31 downto 0); -- data out
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cpu_data_o : out std_ulogic_vector(31 downto 0); -- data out
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-- Access Control ------------------------------------------------------------------------
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-- Access Control ------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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acc_en <= '1' when (cpu_addr_i(hi_abb_c downto lo_abb_c) = dm_base_c(hi_abb_c downto lo_abb_c)) else '0';
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acc_en <= '1' when (cpu_addr_i(hi_abb_c downto lo_abb_c) = dm_base_c(hi_abb_c downto lo_abb_c)) else '0';
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maddr <= cpu_addr_i(lo_abb_c-1 downto lo_abb_c-2); -- (sub-)module select address
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maddr <= cpu_addr_i(lo_abb_c-1 downto lo_abb_c-2); -- (sub-)module select address
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rden <= acc_en and cpu_rden_i;
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rden <= acc_en and cpu_debug_i and cpu_rden_i; -- allow access only when in debug mode
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wren <= acc_en and cpu_wren_i;
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wren <= acc_en and cpu_debug_i and cpu_wren_i; -- allow access only when in debug mode
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-- Write Access ---------------------------------------------------------------------------
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-- Write Access ---------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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write_access: process(clk_i)
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write_access: process(clk_i)
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