| Line 35... |
Line 35... |
-- # https://github.com/stnolting/riscv-debug-dtm (c) Stephan Nolting #
|
-- # https://github.com/stnolting/riscv-debug-dtm (c) Stephan Nolting #
|
-- #################################################################################################
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-- #################################################################################################
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.numeric_std.all;
|
|
|
|
entity neorv32_debug_dtm is
|
entity neorv32_debug_dtm is
|
generic (
|
generic (
|
IDCODE_VERSION : std_ulogic_vector(03 downto 0); -- version
|
IDCODE_VERSION : std_ulogic_vector(03 downto 0); -- version
|
IDCODE_PARTID : std_ulogic_vector(15 downto 0); -- part number
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IDCODE_PARTID : std_ulogic_vector(15 downto 0); -- part number
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| Line 70... |
Line 69... |
end neorv32_debug_dtm;
|
end neorv32_debug_dtm;
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|
|
architecture neorv32_debug_dtm_rtl of neorv32_debug_dtm is
|
architecture neorv32_debug_dtm_rtl of neorv32_debug_dtm is
|
|
|
-- DMI Configuration (fixed!) --
|
-- DMI Configuration (fixed!) --
|
constant dmi_idle_c : std_ulogic_vector(02 downto 0) := "010"; -- minimum number if idle cycles
|
constant dmi_idle_c : std_ulogic_vector(02 downto 0) := "000"; -- no idle cycles required
|
constant dmi_version_c : std_ulogic_vector(03 downto 0) := "0001"; -- version (0.13)
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constant dmi_version_c : std_ulogic_vector(03 downto 0) := "0001"; -- version (0.13)
|
constant dmi_abits_c : std_ulogic_vector(05 downto 0) := "000111"; -- number of DMI address bits (7)
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constant dmi_abits_c : std_ulogic_vector(05 downto 0) := "000111"; -- number of DMI address bits (7)
|
|
|
|
-- tap JTAG signal synchronizer --
|
|
type tap_sync_t is record
|
|
-- internal --
|
|
trst_ff : std_ulogic_vector(2 downto 0);
|
|
tck_ff : std_ulogic_vector(2 downto 0);
|
|
tdi_ff : std_ulogic_vector(2 downto 0);
|
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tms_ff : std_ulogic_vector(2 downto 0);
|
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-- external --
|
|
trst : std_ulogic;
|
|
tck_rising : std_ulogic;
|
|
tck_falling : std_ulogic;
|
|
tdi : std_ulogic;
|
|
tdo : std_ulogic;
|
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tms : std_ulogic;
|
|
end record;
|
|
signal tap_sync : tap_sync_t;
|
|
|
-- tap controller - fsm --
|
-- tap controller - fsm --
|
type tap_ctrl_state_t is (LOGIC_RESET, DR_SCAN, DR_CAPTURE, DR_SHIFT, DR_EXIT1, DR_PAUSE, DR_EXIT2, DR_UPDATE,
|
type tap_ctrl_state_t is (LOGIC_RESET, DR_SCAN, DR_CAPTURE, DR_SHIFT, DR_EXIT1, DR_PAUSE, DR_EXIT2, DR_UPDATE,
|
RUN_IDLE, IR_SCAN, IR_CAPTURE, IR_SHIFT, IR_EXIT1, IR_PAUSE, IR_EXIT2, IR_UPDATE);
|
RUN_IDLE, IR_SCAN, IR_CAPTURE, IR_SHIFT, IR_EXIT1, IR_PAUSE, IR_EXIT2, IR_UPDATE);
|
type tap_ctrl_t is record
|
type tap_ctrl_t is record
|
state : tap_ctrl_state_t;
|
state : tap_ctrl_state_t;
|
state_prev : tap_ctrl_state_t;
|
state_prev : tap_ctrl_state_t;
|
trst_sync : std_ulogic_vector(01 downto 0);
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tck_sync : std_ulogic_vector(02 downto 0);
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tdi_sync : std_ulogic_vector(01 downto 0);
|
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tdo_sync : std_ulogic;
|
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tms_sync : std_ulogic_vector(01 downto 0);
|
|
end record;
|
end record;
|
signal tap_ctrl : tap_ctrl_t;
|
signal tap_ctrl : tap_ctrl_t;
|
|
|
-- tap registers --
|
-- tap registers --
|
type tap_reg_t is record
|
type tap_reg_t is record
|
| Line 116... |
Line 127... |
end record;
|
end record;
|
signal dmi_ctrl : dmi_ctrl_t;
|
signal dmi_ctrl : dmi_ctrl_t;
|
|
|
begin
|
begin
|
|
|
|
-- JTAG Signal Synchronizer ---------------------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
tap_synchronizer: process(rstn_i, clk_i)
|
|
begin
|
|
if rising_edge(clk_i) then
|
|
tap_sync.trst_ff <= tap_sync.trst_ff(1 downto 0) & jtag_trst_i;
|
|
tap_sync.tck_ff <= tap_sync.tck_ff( 1 downto 0) & jtag_tck_i;
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tap_sync.tdi_ff <= tap_sync.tdi_ff( 1 downto 0) & jtag_tdi_i;
|
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tap_sync.tms_ff <= tap_sync.tms_ff( 1 downto 0) & jtag_tms_i;
|
|
if (tap_sync.tck_falling = '1') then -- update output data TDO on falling edge of TCK
|
|
jtag_tdo_o <= tap_sync.tdo;
|
|
end if;
|
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end if;
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end process tap_synchronizer;
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|
|
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-- JTAG reset --
|
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tap_sync.trst <= '0' when (tap_sync.trst_ff(2 downto 1) = "00") else '1';
|
|
|
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-- JTAG clock edge --
|
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tap_sync.tck_rising <= '1' when (tap_sync.tck_ff(2 downto 1) = "01") else '0';
|
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tap_sync.tck_falling <= '1' when (tap_sync.tck_ff(2 downto 1) = "10") else '0';
|
|
|
|
-- JTAG test mode select --
|
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tap_sync.tms <= tap_sync.tms_ff(2);
|
|
|
|
-- JTAG serial data input --
|
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tap_sync.tdi <= tap_sync.tdi_ff(2);
|
|
|
|
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-- Tap Control FSM ------------------------------------------------------------------------
|
-- Tap Control FSM ------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
tap_control: process(rstn_i, clk_i)
|
tap_control: process(rstn_i, clk_i)
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
tap_ctrl.trst_sync <= (others => '0');
|
|
tap_ctrl.tck_sync <= (others => '0');
|
|
tap_ctrl.tdi_sync <= (others => '0');
|
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tap_ctrl.tms_sync <= (others => '0');
|
|
jtag_tdo_o <= '0';
|
|
--
|
|
tap_ctrl.state <= LOGIC_RESET;
|
tap_ctrl.state <= LOGIC_RESET;
|
tap_ctrl.state_prev <= LOGIC_RESET;
|
tap_ctrl.state_prev <= LOGIC_RESET;
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
-- synchronizer --
|
|
tap_ctrl.trst_sync <= tap_ctrl.trst_sync(0) & jtag_trst_i;
|
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tap_ctrl.tck_sync <= tap_ctrl.tck_sync(1 downto 0) & jtag_tck_i;
|
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tap_ctrl.tdi_sync <= tap_ctrl.tdi_sync(0) & jtag_tdi_i;
|
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tap_ctrl.tms_sync <= tap_ctrl.tms_sync(0) & jtag_tms_i;
|
|
jtag_tdo_o <= tap_ctrl.tdo_sync;
|
|
|
|
-- state machine --
|
|
tap_ctrl.state_prev <= tap_ctrl.state;
|
tap_ctrl.state_prev <= tap_ctrl.state;
|
if (tap_ctrl.trst_sync(1) = '0') then -- reset
|
if (tap_sync.trst = '0') then -- reset
|
tap_ctrl.state <= LOGIC_RESET;
|
tap_ctrl.state <= LOGIC_RESET;
|
elsif (tap_ctrl.tck_sync(2) = '0') and (tap_ctrl.tck_sync(1) = '1') then -- clock pulse (trigger on rising edge)
|
elsif (tap_sync.tck_rising = '1') then -- clock pulse (evaluate TMS on the rising edge of TCK)
|
case tap_ctrl.state is -- JTAG state machine
|
case tap_ctrl.state is -- JTAG state machine
|
when LOGIC_RESET => if (tap_ctrl.tms_sync(1) = '0') then tap_ctrl.state <= RUN_IDLE; else tap_ctrl.state <= LOGIC_RESET; end if;
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when LOGIC_RESET => if (tap_sync.tms = '0') then tap_ctrl.state <= RUN_IDLE; else tap_ctrl.state <= LOGIC_RESET; end if;
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when RUN_IDLE => if (tap_ctrl.tms_sync(1) = '0') then tap_ctrl.state <= RUN_IDLE; else tap_ctrl.state <= DR_SCAN; end if;
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when RUN_IDLE => if (tap_sync.tms = '0') then tap_ctrl.state <= RUN_IDLE; else tap_ctrl.state <= DR_SCAN; end if;
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when DR_SCAN => if (tap_ctrl.tms_sync(1) = '0') then tap_ctrl.state <= DR_CAPTURE; else tap_ctrl.state <= IR_SCAN; end if;
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when DR_SCAN => if (tap_sync.tms = '0') then tap_ctrl.state <= DR_CAPTURE; else tap_ctrl.state <= IR_SCAN; end if;
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when DR_CAPTURE => if (tap_ctrl.tms_sync(1) = '0') then tap_ctrl.state <= DR_SHIFT; else tap_ctrl.state <= DR_EXIT1; end if;
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when DR_CAPTURE => if (tap_sync.tms = '0') then tap_ctrl.state <= DR_SHIFT; else tap_ctrl.state <= DR_EXIT1; end if;
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when DR_SHIFT => if (tap_ctrl.tms_sync(1) = '0') then tap_ctrl.state <= DR_SHIFT; else tap_ctrl.state <= DR_EXIT1; end if;
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when DR_SHIFT => if (tap_sync.tms = '0') then tap_ctrl.state <= DR_SHIFT; else tap_ctrl.state <= DR_EXIT1; end if;
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when DR_EXIT1 => if (tap_ctrl.tms_sync(1) = '0') then tap_ctrl.state <= DR_PAUSE; else tap_ctrl.state <= DR_UPDATE; end if;
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when DR_EXIT1 => if (tap_sync.tms = '0') then tap_ctrl.state <= DR_PAUSE; else tap_ctrl.state <= DR_UPDATE; end if;
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when DR_PAUSE => if (tap_ctrl.tms_sync(1) = '0') then tap_ctrl.state <= DR_PAUSE; else tap_ctrl.state <= DR_EXIT2; end if;
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when DR_PAUSE => if (tap_sync.tms = '0') then tap_ctrl.state <= DR_PAUSE; else tap_ctrl.state <= DR_EXIT2; end if;
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when DR_EXIT2 => if (tap_ctrl.tms_sync(1) = '0') then tap_ctrl.state <= DR_SHIFT; else tap_ctrl.state <= DR_UPDATE; end if;
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when DR_EXIT2 => if (tap_sync.tms = '0') then tap_ctrl.state <= DR_SHIFT; else tap_ctrl.state <= DR_UPDATE; end if;
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when DR_UPDATE => if (tap_ctrl.tms_sync(1) = '0') then tap_ctrl.state <= RUN_IDLE; else tap_ctrl.state <= DR_SCAN; end if;
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when DR_UPDATE => if (tap_sync.tms = '0') then tap_ctrl.state <= RUN_IDLE; else tap_ctrl.state <= DR_SCAN; end if;
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when IR_SCAN => if (tap_ctrl.tms_sync(1) = '0') then tap_ctrl.state <= IR_CAPTURE; else tap_ctrl.state <= LOGIC_RESET; end if;
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when IR_SCAN => if (tap_sync.tms = '0') then tap_ctrl.state <= IR_CAPTURE; else tap_ctrl.state <= LOGIC_RESET; end if;
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when IR_CAPTURE => if (tap_ctrl.tms_sync(1) = '0') then tap_ctrl.state <= IR_SHIFT; else tap_ctrl.state <= IR_EXIT1; end if;
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when IR_CAPTURE => if (tap_sync.tms = '0') then tap_ctrl.state <= IR_SHIFT; else tap_ctrl.state <= IR_EXIT1; end if;
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when IR_SHIFT => if (tap_ctrl.tms_sync(1) = '0') then tap_ctrl.state <= IR_SHIFT; else tap_ctrl.state <= IR_EXIT1; end if;
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when IR_SHIFT => if (tap_sync.tms = '0') then tap_ctrl.state <= IR_SHIFT; else tap_ctrl.state <= IR_EXIT1; end if;
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when IR_EXIT1 => if (tap_ctrl.tms_sync(1) = '0') then tap_ctrl.state <= IR_PAUSE; else tap_ctrl.state <= IR_UPDATE; end if;
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when IR_EXIT1 => if (tap_sync.tms = '0') then tap_ctrl.state <= IR_PAUSE; else tap_ctrl.state <= IR_UPDATE; end if;
|
when IR_PAUSE => if (tap_ctrl.tms_sync(1) = '0') then tap_ctrl.state <= IR_PAUSE; else tap_ctrl.state <= IR_EXIT2; end if;
|
when IR_PAUSE => if (tap_sync.tms = '0') then tap_ctrl.state <= IR_PAUSE; else tap_ctrl.state <= IR_EXIT2; end if;
|
when IR_EXIT2 => if (tap_ctrl.tms_sync(1) = '0') then tap_ctrl.state <= IR_SHIFT; else tap_ctrl.state <= IR_UPDATE; end if;
|
when IR_EXIT2 => if (tap_sync.tms = '0') then tap_ctrl.state <= IR_SHIFT; else tap_ctrl.state <= IR_UPDATE; end if;
|
when IR_UPDATE => if (tap_ctrl.tms_sync(1) = '0') then tap_ctrl.state <= RUN_IDLE; else tap_ctrl.state <= DR_SCAN; end if;
|
when IR_UPDATE => if (tap_sync.tms = '0') then tap_ctrl.state <= RUN_IDLE; else tap_ctrl.state <= DR_SCAN; end if;
|
when others => tap_ctrl.state <= LOGIC_RESET;
|
when others => tap_ctrl.state <= LOGIC_RESET;
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process tap_control;
|
end process tap_control;
|
| Line 171... |
Line 197... |
-- Tap Register Access --------------------------------------------------------------------
|
-- Tap Register Access --------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
reg_access: process(clk_i)
|
reg_access: process(clk_i)
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
if (tap_ctrl.trst_sync(1) = '0') then -- reset
|
-- serial data input --
|
tap_reg.ireg <= "00001"; -- IDCODE
|
if (tap_sync.tck_rising = '1') then -- clock pulse (evaluate TDI on rising edge of TCK)
|
elsif (tap_ctrl.tck_sync(2) = '0') and (tap_ctrl.tck_sync(1) = '1') then -- clock pulse (trigger on rising edge)
|
|
|
|
-- instruction register --
|
-- instruction register --
|
if (tap_ctrl.state = LOGIC_RESET) then -- reset
|
if (tap_ctrl.state = LOGIC_RESET) or (tap_ctrl.state = IR_CAPTURE) then -- reset or preload phase
|
tap_reg.ireg <= "00001"; -- IDCODE
|
|
elsif (tap_ctrl.state = IR_CAPTURE) then -- preload phase
|
|
tap_reg.ireg <= "00001"; -- IDCODE
|
tap_reg.ireg <= "00001"; -- IDCODE
|
elsif (tap_ctrl.state = IR_SHIFT) then -- access phase
|
elsif (tap_ctrl.state = IR_SHIFT) then -- access phase
|
tap_reg.ireg <= tap_ctrl.tdi_sync(1) & tap_reg.ireg(tap_reg.ireg'left downto 1);
|
tap_reg.ireg <= tap_sync.tdi & tap_reg.ireg(tap_reg.ireg'left downto 1);
|
end if;
|
end if;
|
|
|
-- data register --
|
-- data register --
|
if (tap_ctrl.state = DR_CAPTURE) then -- preload phase
|
if (tap_ctrl.state = DR_CAPTURE) then -- preload phase
|
case tap_reg.ireg is
|
case tap_reg.ireg is
|
when "00001" => tap_reg.idcode <= IDCODE_VERSION & IDCODE_PARTID & IDCODE_MANID & '1'; -- IDCODE (LBS has to be always set!)
|
when "00001" => tap_reg.idcode <= IDCODE_VERSION & IDCODE_PARTID & IDCODE_MANID & '1'; -- IDCODE (LSB has to be always set!)
|
when "10000" => tap_reg.dtmcs <= tap_reg.dtmcs_nxt;-- dtmcs
|
when "10000" => tap_reg.dtmcs <= tap_reg.dtmcs_nxt;-- dtmcs
|
when "10001" => tap_reg.dmi <= tap_reg.dmi_nxt; -- dmi
|
when "10001" => tap_reg.dmi <= tap_reg.dmi_nxt; -- dmi
|
when others => tap_reg.bypass <= '0'; -- BYPASS
|
when others => tap_reg.bypass <= '0'; -- BYPASS
|
end case;
|
end case;
|
elsif (tap_ctrl.state = DR_SHIFT) then -- access phase
|
elsif (tap_ctrl.state = DR_SHIFT) then -- access phase
|
case tap_reg.ireg is
|
case tap_reg.ireg is
|
when "00001" => tap_reg.idcode <= tap_ctrl.tdi_sync(1) & tap_reg.idcode(tap_reg.idcode'left downto 1); -- IDCODE
|
when "00001" => tap_reg.idcode <= tap_sync.tdi & tap_reg.idcode(tap_reg.idcode'left downto 1); -- IDCODE
|
when "10000" => tap_reg.dtmcs <= tap_ctrl.tdi_sync(1) & tap_reg.dtmcs(tap_reg.dtmcs'left downto 1); -- dtmcs
|
when "10000" => tap_reg.dtmcs <= tap_sync.tdi & tap_reg.dtmcs(tap_reg.dtmcs'left downto 1); -- dtmcs
|
when "10001" => tap_reg.dmi <= tap_ctrl.tdi_sync(1) & tap_reg.dmi(tap_reg.dmi'left downto 1); -- dmi
|
when "10001" => tap_reg.dmi <= tap_sync.tdi & tap_reg.dmi(tap_reg.dmi'left downto 1); -- dmi
|
when others => tap_reg.bypass <= tap_ctrl.tdi_sync(1); -- BYPASS
|
when others => tap_reg.bypass <= tap_sync.tdi; -- BYPASS
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
-- serial data output --
|
-- serial data output --
|
if (tap_ctrl.state = IR_SHIFT) then
|
if (tap_ctrl.state = IR_SHIFT) then
|
tap_ctrl.tdo_sync <= tap_reg.ireg(0);
|
tap_sync.tdo <= tap_reg.ireg(0);
|
else
|
else
|
case tap_reg.ireg is
|
case tap_reg.ireg is
|
when "00001" => tap_ctrl.tdo_sync <= tap_reg.idcode(0); -- IDCODE
|
when "00001" => tap_sync.tdo <= tap_reg.idcode(0); -- IDCODE
|
when "10000" => tap_ctrl.tdo_sync <= tap_reg.dtmcs(0); -- dtmcs
|
when "10000" => tap_sync.tdo <= tap_reg.dtmcs(0); -- dtmcs
|
when "10001" => tap_ctrl.tdo_sync <= tap_reg.dmi(0); -- dmi
|
when "10001" => tap_sync.tdo <= tap_reg.dmi(0); -- dmi
|
when others => tap_ctrl.tdo_sync <= tap_reg.bypass; -- BYPASS
|
when others => tap_sync.tdo <= tap_reg.bypass; -- BYPASS
|
end case;
|
end case;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process reg_access;
|
end process reg_access;
|
|
|
|
|
-- Debug Module Interface -----------------------------------------------------------------
|
-- Debug Module Interface -----------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
|
|
-- DTM Control and Status Register (dtmcs) --
|
|
tap_reg.dtmcs_nxt(31 downto 18) <= (others => '0'); -- unused
|
|
tap_reg.dtmcs_nxt(17) <= '0'; -- dmihardreset, always reads as zero
|
|
tap_reg.dtmcs_nxt(16) <= '0'; -- dmireset, always reads as zero
|
|
tap_reg.dtmcs_nxt(15) <= '0'; -- unused
|
|
tap_reg.dtmcs_nxt(14 downto 12) <= dmi_idle_c; -- minimum number if idle cycles
|
|
tap_reg.dtmcs_nxt(11 downto 10) <= tap_reg.dmi_nxt(1 downto 0); -- dmistat
|
|
tap_reg.dtmcs_nxt(09 downto 04) <= dmi_abits_c; -- number of DMI address bits
|
|
tap_reg.dtmcs_nxt(03 downto 00) <= dmi_version_c; -- version
|
|
|
|
|
|
-- Debug Module Interface Access Register (dmi) --
|
|
dmi_controller: process(rstn_i, clk_i)
|
dmi_controller: process(rstn_i, clk_i)
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
dmi_ctrl.state <= DMI_IDLE;
|
dmi_ctrl.state <= DMI_IDLE;
|
dmi_ctrl.dmihardreset <= '1';
|
dmi_ctrl.dmihardreset <= '1';
|
| Line 261... |
Line 271... |
else
|
else
|
case dmi_ctrl.state is
|
case dmi_ctrl.state is
|
|
|
when DMI_IDLE => -- waiting for new request
|
when DMI_IDLE => -- waiting for new request
|
if (tap_ctrl.state = DR_UPDATE) and (tap_ctrl.state_prev /= DR_UPDATE) and (tap_reg.ireg = "10001") then -- update <dmi>
|
if (tap_ctrl.state = DR_UPDATE) and (tap_ctrl.state_prev /= DR_UPDATE) and (tap_reg.ireg = "10001") then -- update <dmi>
|
case tap_reg.dmi(1 downto 0) is -- op field
|
if (tap_reg.dmi(1 downto 0) = "01") then -- read
|
when "01" => dmi_ctrl.state <= DMI_READ_WAIT; -- read
|
dmi_ctrl.state <= DMI_READ_WAIT;
|
when "10" => dmi_ctrl.state <= DMI_WRITE_WAIT; -- write
|
elsif (tap_reg.dmi(1 downto 0) = "10") then -- write
|
when others => NULL;
|
dmi_ctrl.state <= DMI_WRITE_WAIT;
|
end case;
|
end if;
|
dmi_ctrl.addr <= tap_reg.dmi(40 downto 34);
|
dmi_ctrl.addr <= tap_reg.dmi(40 downto 34);
|
dmi_ctrl.wdata <= tap_reg.dmi(33 downto 02);
|
dmi_ctrl.wdata <= tap_reg.dmi(33 downto 02);
|
end if;
|
end if;
|
|
|
|
|
when DMI_READ_WAIT => -- wait for DMI to become ready
|
when DMI_READ_WAIT => -- wait for DMI to become ready
|
if (dmi_req_ready_i = '1') then
|
if (dmi_req_ready_i = '1') then
|
dmi_ctrl.state <= DMI_READ;
|
dmi_ctrl.state <= DMI_READ;
|
end if;
|
end if;
|
|
|
| Line 285... |
Line 296... |
dmi_ctrl.rdata <= dmi_resp_data_i;
|
dmi_ctrl.rdata <= dmi_resp_data_i;
|
dmi_ctrl.err <= dmi_ctrl.err or dmi_resp_err_i; -- sticky error
|
dmi_ctrl.err <= dmi_ctrl.err or dmi_resp_err_i; -- sticky error
|
dmi_ctrl.state <= DMI_IDLE;
|
dmi_ctrl.state <= DMI_IDLE;
|
end if;
|
end if;
|
|
|
|
|
when DMI_WRITE_WAIT => -- wait for DMI to become ready
|
when DMI_WRITE_WAIT => -- wait for DMI to become ready
|
if (dmi_req_ready_i = '1') then
|
if (dmi_req_ready_i = '1') then
|
dmi_ctrl.state <= DMI_WRITE;
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dmi_ctrl.state <= DMI_WRITE;
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end if;
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end if;
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| Line 299... |
Line 311... |
if (dmi_resp_valid_i = '1') then
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if (dmi_resp_valid_i = '1') then
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dmi_ctrl.err <= dmi_ctrl.err or dmi_resp_err_i; -- sticky error
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dmi_ctrl.err <= dmi_ctrl.err or dmi_resp_err_i; -- sticky error
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dmi_ctrl.state <= DMI_IDLE;
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dmi_ctrl.state <= DMI_IDLE;
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end if;
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end if;
|
|
|
|
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when others => -- undefined
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when others => -- undefined
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dmi_ctrl.state <= DMI_IDLE;
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dmi_ctrl.state <= DMI_IDLE;
|
|
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end case;
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end case;
|
-- override sticky error flag --
|
-- clear sticky error flag --
|
if (dmi_ctrl.dmireset = '1') then
|
if (dmi_ctrl.dmireset = '1') then
|
dmi_ctrl.err <= '0';
|
dmi_ctrl.err <= '0';
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end if;
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end if;
|
end if;
|
end if;
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end if;
|
end if;
|
end process dmi_controller;
|
end process dmi_controller;
|
|
|
|
-- DTM Control and Status Register (dtmcs) --
|
|
tap_reg.dtmcs_nxt(31 downto 18) <= (others => '0'); -- unused
|
|
tap_reg.dtmcs_nxt(17) <= '0'; -- dmihardreset, always reads as zero
|
|
tap_reg.dtmcs_nxt(16) <= '0'; -- dmireset, always reads as zero
|
|
tap_reg.dtmcs_nxt(15) <= '0'; -- unused
|
|
tap_reg.dtmcs_nxt(14 downto 12) <= dmi_idle_c; -- minimum number of idle cycles
|
|
tap_reg.dtmcs_nxt(11 downto 10) <= tap_reg.dmi_nxt(1 downto 0); -- dmistat
|
|
tap_reg.dtmcs_nxt(09 downto 04) <= dmi_abits_c; -- number of DMI address bits
|
|
tap_reg.dtmcs_nxt(03 downto 00) <= dmi_version_c; -- version
|
|
|
-- DMI register read access --
|
-- DMI register read access --
|
tap_reg.dmi_nxt(40 downto 34) <= dmi_ctrl.addr; -- address
|
tap_reg.dmi_nxt(40 downto 34) <= dmi_ctrl.addr; -- address
|
tap_reg.dmi_nxt(33 downto 02) <= dmi_ctrl.rdata; -- read data
|
tap_reg.dmi_nxt(33 downto 02) <= dmi_ctrl.rdata; -- read data
|
tap_reg.dmi_nxt(01 downto 00) <= "11" when (dmi_ctrl.state /= DMI_IDLE) else (dmi_ctrl.err & '0'); -- status
|
tap_reg.dmi_nxt(01 downto 00) <= "11" when (dmi_ctrl.state /= DMI_IDLE) else (dmi_ctrl.err & '0'); -- status
|
|
|
