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library neorv32;
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library neorv32;
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use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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entity neorv32_fifo is
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entity neorv32_fifo is
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generic (
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generic (
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FIFO_DEPTH : natural := 4; -- number of fifo entries; has to be a power of two; min 1
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FIFO_DEPTH : natural; -- number of fifo entries; has to be a power of two; min 1
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FIFO_WIDTH : natural := 32; -- size of data elements in fifo
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FIFO_WIDTH : natural; -- size of data elements in fifo
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FIFO_RSYNC : boolean := false; -- false = async read; true = sync read
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FIFO_RSYNC : boolean; -- false = async read; true = sync read
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FIFO_SAFE : boolean := false -- true = allow read/write only if data available
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FIFO_SAFE : boolean -- true = allow read/write only if entry available
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);
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);
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port (
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port (
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-- control --
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-- control --
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clk_i : in std_ulogic; -- clock, rising edge
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clk_i : in std_ulogic; -- clock, rising edge
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rstn_i : in std_ulogic; -- async reset, low-active
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rstn_i : in std_ulogic; -- async reset, low-active
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clear_i : in std_ulogic; -- sync reset, high-active
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clear_i : in std_ulogic; -- sync reset, high-active
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level_o : out std_ulogic_vector(index_size_f(FIFO_DEPTH) downto 0); -- fill level
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-- write port --
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-- write port --
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wdata_i : in std_ulogic_vector(FIFO_WIDTH-1 downto 0); -- write data
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wdata_i : in std_ulogic_vector(FIFO_WIDTH-1 downto 0); -- write data
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we_i : in std_ulogic; -- write enable
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we_i : in std_ulogic; -- write enable
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free_o : out std_ulogic; -- at least one entry is free when set
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free_o : out std_ulogic; -- at least one entry is free when set
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-- read port --
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-- read port --
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type fifo_t is record
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type fifo_t is record
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we : std_ulogic; -- write enable
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we : std_ulogic; -- write enable
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re : std_ulogic; -- read enable
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re : std_ulogic; -- read enable
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w_pnt : std_ulogic_vector(index_size_f(FIFO_DEPTH) downto 0); -- write pointer
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w_pnt : std_ulogic_vector(index_size_f(FIFO_DEPTH) downto 0); -- write pointer
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r_pnt : std_ulogic_vector(index_size_f(FIFO_DEPTH) downto 0); -- read pointer
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r_pnt : std_ulogic_vector(index_size_f(FIFO_DEPTH) downto 0); -- read pointer
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level : std_ulogic_vector(index_size_f(FIFO_DEPTH) downto 0); -- fill count
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data : fifo_data_t; -- fifo memory
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data : fifo_data_t; -- fifo memory
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datas : std_ulogic_vector(FIFO_WIDTH-1 downto 0);
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match : std_ulogic;
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match : std_ulogic;
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empty : std_ulogic;
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empty : std_ulogic;
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full : std_ulogic;
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full : std_ulogic;
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free : std_ulogic;
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free : std_ulogic;
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avail : std_ulogic;
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avail : std_ulogic;
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end if;
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end if;
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end if;
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end if;
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end process fifo_control;
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end process fifo_control;
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-- status --
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-- status --
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fifo.match <= '1' when (fifo.r_pnt(fifo.r_pnt'left-1 downto 0) = fifo.w_pnt(fifo.w_pnt'left-1 downto 0)) else '0';
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fifo.match <= '1' when (fifo.r_pnt(fifo.r_pnt'left-1 downto 0) = fifo.w_pnt(fifo.w_pnt'left-1 downto 0)) or (FIFO_DEPTH = 1) else '0';
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fifo.full <= '1' when (fifo.r_pnt(fifo.r_pnt'left) /= fifo.w_pnt(fifo.w_pnt'left)) and (fifo.match = '1') else '0';
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fifo.full <= '1' when (fifo.r_pnt(fifo.r_pnt'left) /= fifo.w_pnt(fifo.w_pnt'left)) and (fifo.match = '1') else '0';
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fifo.empty <= '1' when (fifo.r_pnt(fifo.r_pnt'left) = fifo.w_pnt(fifo.w_pnt'left)) and (fifo.match = '1') else '0';
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fifo.empty <= '1' when (fifo.r_pnt(fifo.r_pnt'left) = fifo.w_pnt(fifo.w_pnt'left)) and (fifo.match = '1') else '0';
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fifo.free <= not fifo.full;
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fifo.free <= not fifo.full;
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fifo.avail <= not fifo.empty;
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fifo.avail <= not fifo.empty;
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fifo.level <= std_ulogic_vector(to_unsigned(FIFO_DEPTH, fifo.level'length)) when (fifo.full = '1') else std_ulogic_vector(unsigned(fifo.w_pnt) - unsigned(fifo.r_pnt));
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-- status output --
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-- status output --
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level_o <= fifo.level;
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free_o <= fifo.free;
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free_o <= fifo.free;
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avail_o <= fifo.avail;
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avail_o <= fifo.avail;
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-- FIFO Memory ----------------------------------------------------------------------------
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-- FIFO Memory ----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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fifo_memory_write: process(clk_i)
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fifo_memory_write: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if (fifo.we = '1') then
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if (fifo.we = '1') then
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if (FIFO_DEPTH = 1) then
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fifo.datas <= wdata_i;
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else
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fifo.data(to_integer(unsigned(fifo.w_pnt(fifo.w_pnt'left-1 downto 0)))) <= wdata_i;
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fifo.data(to_integer(unsigned(fifo.w_pnt(fifo.w_pnt'left-1 downto 0)))) <= wdata_i;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process fifo_memory_write;
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end process fifo_memory_write;
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-- asynchronous read --
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-- asynchronous read --
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fifo_read_async:
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fifo_read_async:
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if (FIFO_RSYNC = false) generate
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if (FIFO_RSYNC = false) generate
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rdata_o <= fifo.data(to_integer(unsigned(fifo.r_pnt(fifo.r_pnt'left-1 downto 0))));
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rdata_o <= fifo.datas when (FIFO_DEPTH = 1) else fifo.data(to_integer(unsigned(fifo.r_pnt(fifo.r_pnt'left-1 downto 0))));
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end generate;
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end generate;
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-- synchronous read --
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-- synchronous read --
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fifo_read_sync:
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fifo_read_sync:
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if (FIFO_RSYNC = true) generate
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if (FIFO_RSYNC = true) generate
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fifo_memory_read: process(clk_i)
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fifo_memory_read: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if (fifo.re = '1') then
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if (fifo.re = '1') then
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if (FIFO_DEPTH = 1) then
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rdata_o <= fifo.datas;
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else
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rdata_o <= fifo.data(to_integer(unsigned(fifo.r_pnt(fifo.r_pnt'left-1 downto 0))));
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rdata_o <= fifo.data(to_integer(unsigned(fifo.r_pnt(fifo.r_pnt'left-1 downto 0))));
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end if;
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end if;
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end if;
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end if;
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end if;
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end process fifo_memory_read;
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end process fifo_memory_read;
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end generate;
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end generate;
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end neorv32_fifo_rtl;
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end neorv32_fifo_rtl;
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