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Line 1... |
-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - General Purpose Parallel Input/Output Port (GPIO) >> #
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-- # << NEORV32 - General Purpose Parallel Input/Output Port (GPIO) >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # 16-bit parallel input & output unit. Any pin-change (HI->LO or LO->HI) triggers the IRQ. #
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-- # 32-bit parallel input & output unit. Any pin change (HI->LO or LO->HI) triggers an IRQ. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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| Line 46... |
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-- host access --
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-- host access --
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clk_i : in std_ulogic; -- global clock line
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clk_i : in std_ulogic; -- global clock line
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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rden_i : in std_ulogic; -- read enable
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rden_i : in std_ulogic; -- read enable
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wren_i : in std_ulogic; -- write enable
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wren_i : in std_ulogic; -- write enable
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ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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ack_o : out std_ulogic; -- transfer acknowledge
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ack_o : out std_ulogic; -- transfer acknowledge
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-- parallel io --
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-- parallel io --
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gpio_o : out std_ulogic_vector(15 downto 0);
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gpio_o : out std_ulogic_vector(31 downto 0);
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gpio_i : in std_ulogic_vector(15 downto 0);
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gpio_i : in std_ulogic_vector(31 downto 0);
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-- interrupt --
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-- interrupt --
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irq_o : out std_ulogic
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irq_o : out std_ulogic
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);
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);
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end neorv32_gpio;
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end neorv32_gpio;
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-- access control --
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-- access control --
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signal acc_en : std_ulogic; -- module access enable
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signal acc_en : std_ulogic; -- module access enable
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signal addr : std_ulogic_vector(31 downto 0); -- access address
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signal addr : std_ulogic_vector(31 downto 0); -- access address
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-- accessible regs --
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-- accessible regs --
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signal din : std_ulogic_vector(15 downto 0); -- r/w
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signal din : std_ulogic_vector(31 downto 0); -- r/w
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signal dout : std_ulogic_vector(15 downto 0); -- r/w
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signal dout : std_ulogic_vector(31 downto 0); -- r/w
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-- misc --
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-- misc --
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signal in_buf, din2 : std_ulogic_vector(15 downto 0);
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signal in_buf : std_ulogic_vector(31 downto 0);
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begin
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begin
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-- Access Control -------------------------------------------------------------------------
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-- Access Control -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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ack_o <= acc_en and (rden_i or wren_i);
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ack_o <= acc_en and (rden_i or wren_i);
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-- write access --
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-- write access --
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if ((acc_en and wren_i) = '1') then
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if ((acc_en and wren_i) = '1') then
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if (addr = gpio_out_addr_c) then
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if (addr = gpio_out_addr_c) then
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for i in 0 to 1 loop
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dout <= data_i;
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if (ben_i(i) = '1') then
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dout(7+i*8 downto 0+i*8) <= data_i(7+i*8 downto 0+i*8);
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end if;
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end loop;
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end if;
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end if;
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end if;
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end if;
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-- read access --
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-- read access --
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data_o <= (others => '0');
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data_o <= (others => '0');
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if ((acc_en and rden_i) = '1') then
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if ((acc_en and rden_i) = '1') then
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if (addr = gpio_in_addr_c) then
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if (addr = gpio_in_addr_c) then
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data_o(15 downto 0) <= din;
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data_o <= din;
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else -- gpio_out_addr_c
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else -- gpio_out_addr_c
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data_o(15 downto 0) <= dout;
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data_o <= dout;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process rw_access;
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end process rw_access;
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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-- input synchronizer --
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-- input synchronizer --
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in_buf <= gpio_i;
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in_buf <= gpio_i;
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din <= in_buf;
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din <= in_buf;
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din2 <= din;
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-- IRQ --
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-- IRQ --
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irq_o <= or_all_f(din xor din2); -- any transition triggers an interrupt
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irq_o <= or_all_f(in_buf xor din); -- any transition triggers an interrupt
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end if;
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end if;
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end process irq_detector;
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end process irq_detector;
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end neorv32_gpio_rtl;
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end neorv32_gpio_rtl;
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