| Line 64... |
Line 64... |
constant lo_abb_c : natural := index_size_f(gpio_size_c); -- low address boundary bit
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constant lo_abb_c : natural := index_size_f(gpio_size_c); -- low address boundary bit
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-- access control --
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-- access control --
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signal acc_en : std_ulogic; -- module access enable
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signal acc_en : std_ulogic; -- module access enable
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signal addr : std_ulogic_vector(31 downto 0); -- access address
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signal addr : std_ulogic_vector(31 downto 0); -- access address
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signal wren : std_ulogic; -- word write enable
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signal rden : std_ulogic; -- read enable
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-- accessible regs --
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-- accessible regs --
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signal din_lo, din_hi : std_ulogic_vector(31 downto 0); -- r/-
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signal din_lo, din_hi : std_ulogic_vector(31 downto 0); -- r/-
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signal dout_lo, dout_hi : std_ulogic_vector(31 downto 0); -- r/w
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signal dout_lo, dout_hi : std_ulogic_vector(31 downto 0); -- r/w
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Line 77... |
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-- Access Control -------------------------------------------------------------------------
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-- Access Control -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = gpio_base_c(hi_abb_c downto lo_abb_c)) else '0';
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = gpio_base_c(hi_abb_c downto lo_abb_c)) else '0';
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addr <= gpio_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
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addr <= gpio_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
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wren <= acc_en and wren_i;
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rden <= acc_en and rden_i;
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-- Read/Write Access ----------------------------------------------------------------------
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-- Read/Write Access ----------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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rw_access: process(clk_i)
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rw_access: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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-- bus handshake --
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-- bus handshake --
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ack_o <= acc_en and (rden_i or wren_i);
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ack_o <= wren or rden;
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-- write access --
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-- write access --
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if ((acc_en and wren_i) = '1') then
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if (wren = '1') then
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if (addr = gpio_out_lo_addr_c) then
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if (addr = gpio_out_lo_addr_c) then
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dout_lo <= data_i;
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dout_lo <= data_i;
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end if;
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end if;
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if (addr = gpio_out_hi_addr_c) then
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if (addr = gpio_out_hi_addr_c) then
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dout_hi <= data_i;
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dout_hi <= data_i;
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Line 105... |
din_lo <= gpio_i(31 downto 00);
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din_lo <= gpio_i(31 downto 00);
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din_hi <= gpio_i(63 downto 32);
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din_hi <= gpio_i(63 downto 32);
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-- read access --
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-- read access --
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data_o <= (others => '0');
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data_o <= (others => '0');
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if ((acc_en and rden_i) = '1') then
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if (rden = '1') then
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case addr is
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case addr(3 downto 2) is
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when gpio_in_lo_addr_c => data_o <= din_lo;
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when "00" => data_o <= din_lo;
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when gpio_in_hi_addr_c => data_o <= din_hi;
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when "01" => data_o <= din_hi;
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when gpio_out_lo_addr_c => data_o <= dout_lo;
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when "10" => data_o <= dout_lo;
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when gpio_out_hi_addr_c => data_o <= dout_hi;
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when others => data_o <= dout_hi;
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when others => data_o <= (others => '0');
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end process rw_access;
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end process rw_access;
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