| Line 72... |
Line 72... |
constant ctrl_en_c : natural := 0; -- r/w: timer enable
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constant ctrl_en_c : natural := 0; -- r/w: timer enable
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constant ctrl_prsc0_c : natural := 1; -- r/w: clock prescaler select bit 0
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constant ctrl_prsc0_c : natural := 1; -- r/w: clock prescaler select bit 0
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constant ctrl_prsc1_c : natural := 2; -- r/w: clock prescaler select bit 1
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constant ctrl_prsc1_c : natural := 2; -- r/w: clock prescaler select bit 1
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constant ctrl_prsc2_c : natural := 3; -- r/w: clock prescaler select bit 2
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constant ctrl_prsc2_c : natural := 3; -- r/w: clock prescaler select bit 2
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constant ctrl_mode_c : natural := 4; -- r/w: mode (0=single-shot, 1=continuous)
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constant ctrl_mode_c : natural := 4; -- r/w: mode (0=single-shot, 1=continuous)
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constant ctrl_alarm_c : natural := 5; -- r/c: alarm flag (interrupt), cleared by writing zero
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--
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--
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signal ctrl : std_ulogic_vector(4 downto 0);
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signal ctrl : std_ulogic_vector(4 downto 0);
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|
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-- access control --
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-- access control --
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signal acc_en : std_ulogic; -- module access enable
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signal acc_en : std_ulogic; -- module access enable
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| Line 94... |
Line 93... |
match : std_ulogic; -- count == thres
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match : std_ulogic; -- count == thres
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cnt_we : std_ulogic; -- write access to count
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cnt_we : std_ulogic; -- write access to count
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end record;
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end record;
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signal timer : timer_t;
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signal timer : timer_t;
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|
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-- interrupt generator --
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-- interrupt detector --
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type irq_t is record
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signal irq_detect : std_ulogic_vector(1 downto 0);
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pending : std_ulogic; -- pending interrupt request
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detect : std_ulogic_vector(1 downto 0); -- rising-edge detector
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clearn : std_ulogic; -- clear/ack IRQ request, active-low
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end record;
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signal irq : irq_t;
|
|
|
|
begin
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begin
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|
|
-- Access Control -------------------------------------------------------------------------
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-- Access Control -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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| Line 121... |
Line 115... |
if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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-- bus access acknowledge --
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-- bus access acknowledge --
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ack_o <= rden or wren;
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ack_o <= rden or wren;
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|
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-- write access --
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-- write access --
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irq.clearn <= '1';
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timer.cnt_we <= '0';
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timer.cnt_we <= '0';
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if (wren = '1') then
|
if (wren = '1') then
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if (addr = gptmr_ctrl_addr_c) then -- control register
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if (addr = gptmr_ctrl_addr_c) then -- control register
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ctrl(ctrl_en_c) <= data_i(ctrl_en_c);
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ctrl(ctrl_en_c) <= data_i(ctrl_en_c);
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ctrl(ctrl_prsc0_c) <= data_i(ctrl_prsc0_c);
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ctrl(ctrl_prsc0_c) <= data_i(ctrl_prsc0_c);
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ctrl(ctrl_prsc1_c) <= data_i(ctrl_prsc1_c);
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ctrl(ctrl_prsc1_c) <= data_i(ctrl_prsc1_c);
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ctrl(ctrl_prsc2_c) <= data_i(ctrl_prsc2_c);
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ctrl(ctrl_prsc2_c) <= data_i(ctrl_prsc2_c);
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ctrl(ctrl_mode_c) <= data_i(ctrl_mode_c);
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ctrl(ctrl_mode_c) <= data_i(ctrl_mode_c);
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irq.clearn <= data_i(ctrl_alarm_c);
|
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end if;
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end if;
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if (addr = gptmr_thres_addr_c) then -- threshold register
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if (addr = gptmr_thres_addr_c) then -- threshold register
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timer.thres <= data_i;
|
timer.thres <= data_i;
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end if;
|
end if;
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if (addr = gptmr_count_addr_c) then -- counter register
|
if (addr = gptmr_count_addr_c) then -- counter register
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| Line 150... |
Line 142... |
data_o(ctrl_en_c) <= ctrl(ctrl_en_c);
|
data_o(ctrl_en_c) <= ctrl(ctrl_en_c);
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data_o(ctrl_prsc0_c) <= ctrl(ctrl_prsc0_c);
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data_o(ctrl_prsc0_c) <= ctrl(ctrl_prsc0_c);
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data_o(ctrl_prsc1_c) <= ctrl(ctrl_prsc1_c);
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data_o(ctrl_prsc1_c) <= ctrl(ctrl_prsc1_c);
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data_o(ctrl_prsc2_c) <= ctrl(ctrl_prsc2_c);
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data_o(ctrl_prsc2_c) <= ctrl(ctrl_prsc2_c);
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data_o(ctrl_mode_c) <= ctrl(ctrl_mode_c);
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data_o(ctrl_mode_c) <= ctrl(ctrl_mode_c);
|
data_o(ctrl_alarm_c) <= irq.pending;
|
|
when "01" => -- threshold register
|
when "01" => -- threshold register
|
data_o <= timer.thres;
|
data_o <= timer.thres;
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when others => -- counter register
|
when others => -- counter register
|
data_o <= timer.count;
|
data_o <= timer.count;
|
end case;
|
end case;
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| Line 196... |
Line 187... |
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
irq_generator: process(clk_i)
|
irq_generator: process(clk_i)
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
if (ctrl(ctrl_en_c) = '0') then
|
if (ctrl(ctrl_en_c) = '0') then
|
irq.detect <= "00";
|
irq_detect <= "00";
|
irq.pending <= '0';
|
|
else
|
else
|
irq.detect <= irq.detect(0) & timer.match;
|
irq_detect <= irq_detect(0) & timer.match;
|
if (irq.detect = "01") then -- rising edge
|
|
irq.pending <= '1';
|
|
elsif (irq.clearn = '0') then
|
|
irq.pending <= '0';
|
|
end if;
|
|
end if;
|
end if;
|
end if;
|
end if;
|
end process irq_generator;
|
end process irq_generator;
|
|
|
-- IRQ request to CPU --
|
-- IRQ request to CPU --
|
irq_o <= irq.pending;
|
irq_o <= '1' when (irq_detect = "01") else '0';
|
|
|
|
|
end neorv32_gptmr_rtl;
|
end neorv32_gptmr_rtl;
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