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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_icache.vhd] - Diff between revs 53 and 56

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Rev 53 Rev 56
Line 554... Line 554...
        if (set_select = '0') then
        if (set_select = '0') then
          tag_mem_s0(to_integer(unsigned(cache_index))) <= ctrl_acc_addr.tag;
          tag_mem_s0(to_integer(unsigned(cache_index))) <= ctrl_acc_addr.tag;
        else
        else
          tag_mem_s1(to_integer(unsigned(cache_index))) <= ctrl_acc_addr.tag;
          tag_mem_s1(to_integer(unsigned(cache_index))) <= ctrl_acc_addr.tag;
        end if;
        end if;
      else -- read access
      end if;
        tag(0) <= tag_mem_s0(to_integer(unsigned(cache_index)));
        tag(0) <= tag_mem_s0(to_integer(unsigned(cache_index)));
        tag(1) <= tag_mem_s1(to_integer(unsigned(cache_index)));
        tag(1) <= tag_mem_s1(to_integer(unsigned(cache_index)));
      end if;
      end if;
    end if;
 
  end process tag_memory;
  end process tag_memory;
 
 
  -- comparator --
  -- comparator --
  comparator: process(host_acc_addr, tag, valid)
  comparator: process(host_acc_addr, tag, valid)
  begin
  begin
Line 582... Line 581...
  -- -------------------------------------------------------------------------------------------
  -- -------------------------------------------------------------------------------------------
  cache_mem_access: process(clk_i)
  cache_mem_access: process(clk_i)
  begin
  begin
    if rising_edge(clk_i) then
    if rising_edge(clk_i) then
      if (cache_we = '1') then -- write access from control (full-word)
      if (cache_we = '1') then -- write access from control (full-word)
        if (set_select = '0') then
        if (set_select = '0') or (ICACHE_NUM_SETS = 1) then
          cache_data_memory_s0(to_integer(unsigned(cache_addr))) <= ctrl_wdata_i;
          cache_data_memory_s0(to_integer(unsigned(cache_addr))) <= ctrl_wdata_i;
        else
        else
          cache_data_memory_s1(to_integer(unsigned(cache_addr))) <= ctrl_wdata_i;
          cache_data_memory_s1(to_integer(unsigned(cache_addr))) <= ctrl_wdata_i;
        end if;
        end if;
      else -- read access from host (full-word)
      end if;
 
      -- read access from host (full-word) --
        cache_rdata(0) <= cache_data_memory_s0(to_integer(unsigned(cache_addr)));
        cache_rdata(0) <= cache_data_memory_s0(to_integer(unsigned(cache_addr)));
        cache_rdata(1) <= cache_data_memory_s1(to_integer(unsigned(cache_addr)));
        cache_rdata(1) <= cache_data_memory_s1(to_integer(unsigned(cache_addr)));
      end if;
      end if;
    end if;
 
  end process cache_mem_access;
  end process cache_mem_access;
 
 
  -- data output --
  -- data output --
  host_rdata_o <= cache_rdata(0) when (hit(0) = '1') or (ICACHE_NUM_SETS = 1) else cache_rdata(1);
  host_rdata_o <= cache_rdata(0) when (hit(0) = '1') or (ICACHE_NUM_SETS = 1) else cache_rdata(1);
 
 

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