| Line 137... |
Line 137... |
addr_reg : std_ulogic_vector(31 downto 0); -- address register for block download
|
addr_reg : std_ulogic_vector(31 downto 0); -- address register for block download
|
addr_reg_nxt : std_ulogic_vector(31 downto 0);
|
addr_reg_nxt : std_ulogic_vector(31 downto 0);
|
--
|
--
|
re_buf : std_ulogic; -- read request buffer
|
re_buf : std_ulogic; -- read request buffer
|
re_buf_nxt : std_ulogic;
|
re_buf_nxt : std_ulogic;
|
|
--
|
|
clear_buf : std_ulogic; -- clear request buffer
|
|
clear_buf_nxt : std_ulogic;
|
end record;
|
end record;
|
signal ctrl : ctrl_t;
|
signal ctrl : ctrl_t;
|
|
|
begin
|
begin
|
|
|
| Line 161... |
Line 164... |
ctrl_engine_fsm_sync_rst: process(rstn_i, clk_i)
|
ctrl_engine_fsm_sync_rst: process(rstn_i, clk_i)
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
ctrl.state <= S_CACHE_CLEAR;
|
ctrl.state <= S_CACHE_CLEAR;
|
ctrl.re_buf <= '0';
|
ctrl.re_buf <= '0';
|
|
ctrl.clear_buf <= '0';
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
ctrl.state <= ctrl.state_nxt;
|
ctrl.state <= ctrl.state_nxt;
|
ctrl.re_buf <= ctrl.re_buf_nxt;
|
ctrl.re_buf <= ctrl.re_buf_nxt;
|
|
ctrl.clear_buf <= ctrl.clear_buf_nxt;
|
end if;
|
end if;
|
end process ctrl_engine_fsm_sync_rst;
|
end process ctrl_engine_fsm_sync_rst;
|
|
|
-- registers that do not require a specific reset state --
|
-- registers that do not require a specific reset state --
|
ctrl_engine_fsm_sync: process(clk_i)
|
ctrl_engine_fsm_sync: process(clk_i)
|
| Line 184... |
Line 189... |
begin
|
begin
|
-- control defaults --
|
-- control defaults --
|
ctrl.state_nxt <= ctrl.state;
|
ctrl.state_nxt <= ctrl.state;
|
ctrl.addr_reg_nxt <= ctrl.addr_reg;
|
ctrl.addr_reg_nxt <= ctrl.addr_reg;
|
ctrl.re_buf_nxt <= ctrl.re_buf or host_re_i;
|
ctrl.re_buf_nxt <= ctrl.re_buf or host_re_i;
|
|
ctrl.clear_buf_nxt <= ctrl.clear_buf or clear_i; -- buffer clear request from CPU
|
|
|
-- cache defaults --
|
-- cache defaults --
|
cache.clear <= '0';
|
cache.clear <= '0';
|
cache.host_addr <= host_addr_i;
|
cache.host_addr <= host_addr_i;
|
cache.ctrl_en <= '0';
|
cache.ctrl_en <= '0';
|
| Line 213... |
Line 219... |
-- fsm --
|
-- fsm --
|
case ctrl.state is
|
case ctrl.state is
|
|
|
when S_IDLE => -- wait for host access request or cache control operation
|
when S_IDLE => -- wait for host access request or cache control operation
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
if (clear_i = '1') then -- cache control operation?
|
if (ctrl.clear_buf = '1') then -- cache control operation?
|
ctrl.state_nxt <= S_CACHE_CLEAR;
|
ctrl.state_nxt <= S_CACHE_CLEAR;
|
elsif (host_re_i = '1') or (ctrl.re_buf = '1') then -- cache access
|
elsif (host_re_i = '1') or (ctrl.re_buf = '1') then -- cache access
|
ctrl.re_buf_nxt <= '0';
|
ctrl.re_buf_nxt <= '0';
|
ctrl.state_nxt <= S_CACHE_CHECK;
|
ctrl.state_nxt <= S_CACHE_CHECK;
|
end if;
|
end if;
|
|
|
when S_CACHE_CLEAR => -- invalidate all cache entries
|
when S_CACHE_CLEAR => -- invalidate all cache entries
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
|
ctrl.clear_buf_nxt <= '0';
|
cache.clear <= '1';
|
cache.clear <= '1';
|
ctrl.state_nxt <= S_IDLE;
|
ctrl.state_nxt <= S_IDLE;
|
|
|
when S_CACHE_CHECK => -- finalize host access if cache hit
|
when S_CACHE_CHECK => -- finalize host access if cache hit
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
