| Line 51... |
Line 51... |
port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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rstn_i : in std_ulogic; -- global reset, low-active, async
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clear_i : in std_ulogic; -- cache clear
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clear_i : in std_ulogic; -- cache clear
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miss_o : out std_ulogic; -- cache miss
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-- host controller interface --
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-- host controller interface --
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host_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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host_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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host_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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host_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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host_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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host_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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host_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
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host_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
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| Line 283... |
Line 284... |
ctrl.state_nxt <= S_IDLE;
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ctrl.state_nxt <= S_IDLE;
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|
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end case;
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end case;
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end process ctrl_engine_fsm_comb;
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end process ctrl_engine_fsm_comb;
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|
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-- signal cache miss to CPU --
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miss_o <= '1' when (ctrl.state = S_CACHE_MISS) else '0';
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-- Cache Memory ---------------------------------------------------------------------------
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-- Cache Memory ---------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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neorv32_icache_memory_inst: neorv32_icache_memory
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neorv32_icache_memory_inst: neorv32_icache_memory
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generic map (
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generic map (
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