| Line 5... |
Line 5... |
-- # Write mtime.LO first when updating the system time. System time should be written only at #
|
-- # Write mtime.LO first when updating the system time. System time should be written only at #
|
-- # system start. RISC-V spec. exception: The MTIME interrupt is ACKed by the processor itself. #
|
-- # system start. RISC-V spec. exception: The MTIME interrupt is ACKed by the processor itself. #
|
-- # However, the achine time cannot issue a new interrupt until the mtimecmp.HI register is #
|
-- # However, the achine time cannot issue a new interrupt until the mtimecmp.HI register is #
|
-- # written again. #
|
-- # written again. #
|
-- # Note: The 64-bit time and compare system is broken and de-coupled into two 32-bit systems. #
|
-- # Note: The 64-bit time and compare system is broken and de-coupled into two 32-bit systems. #
|
|
-- # Note: The register of this unit can only be written in WORD MODE. #
|
-- # ********************************************************************************************* #
|
-- # ********************************************************************************************* #
|
-- # BSD 3-Clause License #
|
-- # BSD 3-Clause License #
|
-- # #
|
-- # #
|
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
|
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
|
-- # #
|
-- # #
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| Line 56... |
Line 57... |
wren_i : in std_ulogic; -- write enable
|
wren_i : in std_ulogic; -- write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
ack_o : out std_ulogic; -- transfer acknowledge
|
ack_o : out std_ulogic; -- transfer acknowledge
|
|
-- time output for CPU --
|
|
time_o : out std_ulogic_vector(63 downto 0); -- current system time
|
-- interrupt --
|
-- interrupt --
|
irq_o : out std_ulogic -- interrupt request
|
irq_o : out std_ulogic -- interrupt request
|
);
|
);
|
end neorv32_mtime;
|
end neorv32_mtime;
|
|
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| Line 73... |
Line 76... |
signal acc_en : std_ulogic; -- module access enable
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signal acc_en : std_ulogic; -- module access enable
|
signal addr : std_ulogic_vector(31 downto 0); -- access address
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signal addr : std_ulogic_vector(31 downto 0); -- access address
|
signal wren : std_ulogic; -- module access enable
|
signal wren : std_ulogic; -- module access enable
|
|
|
-- accessible regs --
|
-- accessible regs --
|
signal mtimecmp : std_ulogic_vector(63 downto 0);
|
signal mtimecmp_lo : std_ulogic_vector(31 downto 0);
|
|
signal mtimecmp_hi : std_ulogic_vector(31 downto 0);
|
signal mtime_lo : std_ulogic_vector(32 downto 0);
|
signal mtime_lo : std_ulogic_vector(32 downto 0);
|
signal mtime_lo_msb_ff : std_ulogic;
|
signal mtime_lo_msb_ff : std_ulogic;
|
signal mtime_hi : std_ulogic_vector(31 downto 0);
|
signal mtime_hi : std_ulogic_vector(31 downto 0);
|
|
|
-- irq control --
|
-- irq control --
|
signal cmp_lo : std_ulogic;
|
signal cmp_lo : std_ulogic;
|
signal cmp_lo_ff : std_ulogic;
|
signal cmp_lo_ff : std_ulogic;
|
signal cmp_hi : std_ulogic;
|
signal cmp_hi : std_ulogic;
|
signal cmp_match_ff : std_ulogic;
|
signal cmp_match_ff : std_ulogic;
|
signal irq_flag : std_ulogic;
|
|
signal irq_flag_ff : std_ulogic;
|
|
|
|
begin
|
begin
|
|
|
-- Access Control -------------------------------------------------------------------------
|
-- Access Control -------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = mtime_base_c(hi_abb_c downto lo_abb_c)) else '0';
|
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = mtime_base_c(hi_abb_c downto lo_abb_c)) else '0';
|
addr <= mtime_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
|
addr <= mtime_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
|
wren <= acc_en and wren_i;
|
wren <= acc_en and wren_i and and_all_f(ben_i);
|
|
|
|
|
-- System Time Update ---------------------------------------------------------------------
|
-- Write Access ---------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
system_time: process(clk_i)
|
wr_access: process(clk_i)
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
if (rstn_i = '0') then
|
-- mtimecmp --
|
mtime_lo <= (others => '0');
|
if (wren = '1') then
|
mtime_hi <= (others => '0');
|
if (addr = mtime_cmp_lo_addr_c) then -- low
|
else
|
mtimecmp_lo <= data_i;
|
-- mtime low --
|
|
mtime_lo <= std_ulogic_vector(unsigned(mtime_lo) + 1);
|
|
mtime_lo_msb_ff <= mtime_lo(mtime_lo'left);
|
|
-- mtime high --
|
|
if ((mtime_lo_msb_ff xor mtime_lo(mtime_lo'left)) = '1') then -- mtime_lo carry?
|
|
mtime_hi <= std_ulogic_vector(unsigned(mtime_hi) + 1);
|
|
end if;
|
end if;
|
|
if (addr = mtime_cmp_hi_addr_c) then -- high
|
|
mtimecmp_hi <= data_i;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process system_time;
|
|
|
|
|
|
-- Write Access ---------------------------------------------------------------------------
|
-- mtime low --
|
-- -------------------------------------------------------------------------------------------
|
if (wren = '1') and (addr = mtime_time_lo_addr_c) then
|
wr_access: process(clk_i)
|
mtime_lo_msb_ff <= '0';
|
begin
|
mtime_lo <= '0' & data_i;
|
if rising_edge(clk_i) then
|
else -- auto increment
|
ack_o <= acc_en and (rden_i or wren_i);
|
mtime_lo_msb_ff <= mtime_lo(mtime_lo'left);
|
-- mtimecmp low --
|
mtime_lo <= std_ulogic_vector(unsigned(mtime_lo) + 1);
|
if (wren = '1') and (addr = mtime_cmp_lo_addr_c) then
|
|
for i in 0 to 3 loop
|
|
if (ben_i(i) = '1') then
|
|
mtimecmp(00+7+i*8 downto 00+0+i*8) <= data_i(7+i*8 downto 0+i*8);
|
|
end if;
|
|
end loop; -- byte enable
|
|
end if;
|
|
|
|
-- mtimecmp high --
|
|
if (wren = '1') and (addr = mtime_cmp_hi_addr_c) then
|
|
for i in 0 to 3 loop
|
|
if (ben_i(i) = '1') then
|
|
mtimecmp(32+7+i*8 downto 32+0+i*8) <= data_i(7+i*8 downto 0+i*8);
|
|
end if;
|
end if;
|
end loop; -- byte enable
|
|
|
-- mtime high --
|
|
if (wren = '1') and (addr = mtime_time_hi_addr_c) then
|
|
mtime_hi <= data_i;
|
|
elsif ((mtime_lo_msb_ff xor mtime_lo(mtime_lo'left)) = '1') then -- mtime_lo carry?
|
|
mtime_hi <= std_ulogic_vector(unsigned(mtime_hi) + 1);
|
end if;
|
end if;
|
end if;
|
end if;
|
end process wr_access;
|
end process wr_access;
|
|
|
|
|
-- Read Access ----------------------------------------------------------------------------
|
-- Read Access ----------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
rd_access: process(clk_i)
|
rd_access: process(clk_i)
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
|
ack_o <= acc_en and (rden_i or wren_i);
|
data_o <= (others => '0'); -- default
|
data_o <= (others => '0'); -- default
|
if (rden_i = '1') and (acc_en = '1') then
|
if (rden_i = '1') and (acc_en = '1') then
|
if (addr = mtime_time_lo_addr_c) then -- mtime LOW
|
if (addr = mtime_time_lo_addr_c) then -- mtime LOW
|
data_o <= mtime_lo(31 downto 00);
|
data_o <= mtime_lo(31 downto 00);
|
elsif (addr = mtime_time_hi_addr_c) then -- mtime HIGH
|
elsif (addr = mtime_time_hi_addr_c) then -- mtime HIGH
|
data_o <= mtime_hi;
|
data_o <= mtime_hi;
|
elsif (addr = mtime_cmp_lo_addr_c) then -- mtimecmp LOW
|
elsif (addr = mtime_cmp_lo_addr_c) then -- mtimecmp LOW
|
data_o <= mtimecmp(31 downto 00);
|
data_o <= mtimecmp_lo;
|
else -- (addr = mtime_cmp_hi_addr_c) then -- mtimecmp HIGH
|
else -- (addr = mtime_cmp_hi_addr_c) then -- mtimecmp HIGH
|
data_o <= mtimecmp(63 downto 32);
|
data_o <= mtimecmp_hi;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process rd_access;
|
end process rd_access;
|
|
|
|
-- time output for cpu --
|
|
time_o <= mtime_hi & mtime_lo(31 downto 00);
|
|
|
|
|
-- Comparator -----------------------------------------------------------------------------
|
-- Comparator -----------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
cmp_sync: process(clk_i)
|
cmp_sync: process(clk_i)
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
cmp_lo_ff <= cmp_lo;
|
cmp_lo_ff <= cmp_lo;
|
cmp_match_ff <= cmp_lo_ff and cmp_hi;
|
cmp_match_ff <= cmp_lo_ff and cmp_hi;
|
|
irq_o <= cmp_lo_ff and cmp_hi and (not cmp_match_ff);
|
end if;
|
end if;
|
end process cmp_sync;
|
end process cmp_sync;
|
|
|
-- test words --
|
-- test words --
|
cmp_lo <= '1' when (unsigned(mtime_lo(31 downto 00)) >= unsigned(mtimecmp(31 downto 00))) else '0';
|
cmp_lo <= '1' when (unsigned(mtime_lo(31 downto 00)) >= unsigned(mtimecmp_lo)) else '0';
|
cmp_hi <= '1' when (unsigned(mtime_hi(31 downto 00)) >= unsigned(mtimecmp(63 downto 32))) else '0';
|
cmp_hi <= '1' when (unsigned(mtime_hi(31 downto 00)) >= unsigned(mtimecmp_hi)) else '0';
|
|
|
|
|
-- Interrupt Logic ------------------------------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
irq_ctrl: process(clk_i)
|
|
begin
|
|
if rising_edge(clk_i) then
|
|
if (rstn_i = '0') then
|
|
irq_flag_ff <= '0';
|
|
irq_flag <= '0';
|
|
else
|
|
irq_flag_ff <= irq_flag;
|
|
if (irq_flag = '0') then -- idle
|
|
irq_flag <= '0';
|
|
if (cmp_match_ff = '1') then
|
|
irq_flag <= '1';
|
|
end if;
|
|
elsif (wren = '1') and (addr = mtime_cmp_hi_addr_c) then -- ACK
|
|
irq_flag <= '0';
|
|
end if;
|
|
end if;
|
|
end if;
|
|
end process irq_ctrl;
|
|
|
|
-- irq output to CPU --
|
|
irq_o <= irq_flag and (not irq_flag_ff); -- rising edge detector
|
|
|
|
|
|
end neorv32_mtime_rtl;
|
end neorv32_mtime_rtl;
|
|
|
No newline at end of file
|
No newline at end of file
|
