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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_mtime.vhd] - Diff between revs 26 and 56

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-- #################################################################################################
-- #################################################################################################
-- # << NEORV32 - Machine System Timer (MTIME) >>                                                  #
-- # << NEORV32 - Machine System Timer (MTIME) >>                                                  #
-- # ********************************************************************************************* #
-- # ********************************************************************************************* #
-- # Compatible to RISC-V spec's mtime & mtimecmp.                                                 #
-- # Compatible to RISC-V spec's 64-bit MACHINE system timer including "mtime[h]" & "mtimecmp[h]". #
-- # Write mtime.LO first when updating the system time. System time should be written only at     #
-- # Note: The 64-bit counter and compare system is broken and de-coupled into two 32-bit systems. #
-- # system start. RISC-V spec. exception: The MTIME interrupt is ACKed by the processor itself.   #
 
-- # However, the  achine time cannot issue a new interrupt until the mtimecmp.HI register is      #
 
-- # written again.                                                                                #
 
-- # Note: The 64-bit time and compare system is broken and de-coupled into two 32-bit systems.    #
 
-- # Note: The register of this unit can only be written in WORD MODE.                             #
 
-- # ********************************************************************************************* #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License                                                                          #
-- # BSD 3-Clause License                                                                          #
-- #                                                                                               #
-- #                                                                                               #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved.                                     #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
-- #                                                                                               #
-- #                                                                                               #
-- # Redistribution and use in source and binary forms, with or without modification, are          #
-- # Redistribution and use in source and binary forms, with or without modification, are          #
-- # permitted provided that the following conditions are met:                                     #
-- # permitted provided that the following conditions are met:                                     #
-- #                                                                                               #
-- #                                                                                               #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
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      end if;
      end if;
 
 
      -- mtime high --
      -- mtime high --
      if (wren = '1') and (addr = mtime_time_hi_addr_c) then
      if (wren = '1') and (addr = mtime_time_hi_addr_c) then
        mtime_hi <= data_i;
        mtime_hi <= data_i;
      elsif ((mtime_lo_msb_ff xor mtime_lo(mtime_lo'left)) = '1') then -- mtime_lo carry?
      elsif ((mtime_lo_msb_ff xor mtime_lo(mtime_lo'left)) = '1') then -- auto increment: mtime_lo carry?
        mtime_hi <= std_ulogic_vector(unsigned(mtime_hi) + 1);
        mtime_hi <= std_ulogic_vector(unsigned(mtime_hi) + 1);
      end if;
      end if;
    end if;
    end if;
  end process wr_access;
  end process wr_access;
 
 
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            data_o <= mtime_lo(31 downto 00);
            data_o <= mtime_lo(31 downto 00);
          when mtime_time_hi_addr_c => -- mtime HIGH
          when mtime_time_hi_addr_c => -- mtime HIGH
            data_o <= mtime_hi;
            data_o <= mtime_hi;
          when mtime_cmp_lo_addr_c => -- mtimecmp LOW
          when mtime_cmp_lo_addr_c => -- mtimecmp LOW
            data_o <= mtimecmp_lo;
            data_o <= mtimecmp_lo;
          when others => -- mtime_cmp_hi_addr_c -  mtimecmp HIGH
          when others => -- mtime_cmp_hi_addr_c -- mtimecmp HIGH
            data_o <= mtimecmp_hi;
            data_o <= mtimecmp_hi;
        end case;
        end case;
      end if;
      end if;
    end if;
    end if;
  end process rd_access;
  end process rd_access;

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