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-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - Machine System Timer (MTIME) >> #
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-- # << NEORV32 - Machine System Timer (MTIME) >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # Compatible to RISC-V spec's 64-bit MACHINE system timer including "mtime[h]" & "mtimecmp[h]". #
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-- # Compatible to RISC-V spec's 64-bit MACHINE system timer including "mtime[h]" & "mtimecmp[h]". #
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-- # Note: The 64-bit counter and compare system is broken and de-coupled into two 32-bit systems. #
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-- # Note: The 64-bit counter and compare systems are de-coupled into two 32-bit systems. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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-- access control --
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-- access control --
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signal acc_en : std_ulogic; -- module access enable
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signal acc_en : std_ulogic; -- module access enable
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signal addr : std_ulogic_vector(31 downto 0); -- access address
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signal addr : std_ulogic_vector(31 downto 0); -- access address
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signal wren : std_ulogic; -- module access enable
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signal wren : std_ulogic; -- module access enable
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-- time write access buffer --
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signal wdata_buf : std_ulogic_vector(31 downto 0);
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signal mtime_lo_we : std_ulogic;
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signal mtime_hi_we : std_ulogic;
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-- accessible regs --
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-- accessible regs --
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signal mtimecmp_lo : std_ulogic_vector(31 downto 0);
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signal mtimecmp_lo : std_ulogic_vector(31 downto 0);
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signal mtimecmp_hi : std_ulogic_vector(31 downto 0);
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signal mtimecmp_hi : std_ulogic_vector(31 downto 0);
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signal mtime_lo : std_ulogic_vector(32 downto 0);
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signal mtime_lo : std_ulogic_vector(32 downto 0);
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signal mtime_lo_msb_ff : std_ulogic;
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signal mtime_lo_msb_ff : std_ulogic;
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signal mtime_hi : std_ulogic_vector(31 downto 0);
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signal mtime_hi : std_ulogic_vector(31 downto 0);
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signal inc_hi : std_ulogic_vector(31 downto 0);
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-- irq control --
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-- irq control --
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signal cmp_lo : std_ulogic;
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signal cmp_lo : std_ulogic;
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signal cmp_lo_ff : std_ulogic;
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signal cmp_lo_ff : std_ulogic;
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signal cmp_hi : std_ulogic;
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signal cmp_hi : std_ulogic;
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-- Write Access ---------------------------------------------------------------------------
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-- Write Access ---------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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wr_access: process(clk_i)
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wr_access: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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-- mtimecmp low --
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-- mtimecmp --
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if (wren = '1') and (addr = mtime_cmp_lo_addr_c) then
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if (wren = '1') then
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if (addr = mtime_cmp_lo_addr_c) then
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mtimecmp_lo <= data_i;
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mtimecmp_lo <= data_i;
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end if;
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end if;
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if (addr = mtime_cmp_hi_addr_c) then
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-- mtimecmp high --
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if (wren = '1') and (addr = mtime_cmp_hi_addr_c) then
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mtimecmp_hi <= data_i;
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mtimecmp_hi <= data_i;
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end if;
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end if;
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end if;
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-- mtime access buffer --
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wdata_buf <= data_i;
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mtime_lo_we <= wren and bool_to_ulogic_f(boolean(addr = mtime_time_lo_addr_c));
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mtime_hi_we <= wren and bool_to_ulogic_f(boolean(addr = mtime_time_hi_addr_c));
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-- mtime low --
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-- mtime low --
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if (wren = '1') and (addr = mtime_time_lo_addr_c) then
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if (mtime_lo_we = '1') then -- write access
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mtime_lo_msb_ff <= '0';
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mtime_lo_msb_ff <= '0';
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mtime_lo <= '0' & data_i;
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mtime_lo <= '0' & wdata_buf;
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else -- auto increment
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else -- auto increment
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mtime_lo_msb_ff <= mtime_lo(mtime_lo'left);
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mtime_lo_msb_ff <= mtime_lo(mtime_lo'left);
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mtime_lo <= std_ulogic_vector(unsigned(mtime_lo) + 1);
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mtime_lo <= std_ulogic_vector(unsigned(mtime_lo) + 1);
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end if;
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end if;
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-- mtime high --
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-- mtime high --
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if (wren = '1') and (addr = mtime_time_hi_addr_c) then
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if (mtime_hi_we = '1') then -- write access
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mtime_hi <= data_i;
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mtime_hi <= wdata_buf;
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elsif ((mtime_lo_msb_ff xor mtime_lo(mtime_lo'left)) = '1') then -- auto increment: mtime_lo carry?
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else -- auto increment (if mtime.low overflows)
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mtime_hi <= std_ulogic_vector(unsigned(mtime_hi) + 1);
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mtime_hi <= std_ulogic_vector(unsigned(mtime_hi) + unsigned(inc_hi));
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end if;
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end if;
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end if;
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end if;
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end process wr_access;
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end process wr_access;
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-- mtime.time_HI increment (0 or 1) --
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inc_hi(0) <= mtime_lo_msb_ff xor mtime_lo(mtime_lo'left);
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inc_hi(31 downto 1) <= (others => '0');
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-- Read Access ----------------------------------------------------------------------------
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-- Read Access ----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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rd_access: process(clk_i)
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rd_access: process(clk_i)
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begin
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begin
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