| Line 69... |
Line 69... |
signal acc_en : std_ulogic; -- module access enable
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signal acc_en : std_ulogic; -- module access enable
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signal addr : std_ulogic_vector(31 downto 0); -- access address
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signal addr : std_ulogic_vector(31 downto 0); -- access address
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signal wren : std_ulogic; -- module access enable
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signal wren : std_ulogic; -- module access enable
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-- time write access buffer --
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-- time write access buffer --
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signal wdata_buf : std_ulogic_vector(31 downto 0);
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signal mtime_lo_we : std_ulogic;
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signal mtime_lo_we : std_ulogic;
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signal mtime_hi_we : std_ulogic;
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signal mtime_hi_we : std_ulogic;
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-- accessible regs --
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-- accessible regs --
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signal mtimecmp_lo : std_ulogic_vector(31 downto 0);
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signal mtimecmp_lo : std_ulogic_vector(31 downto 0);
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signal mtimecmp_hi : std_ulogic_vector(31 downto 0);
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signal mtimecmp_hi : std_ulogic_vector(31 downto 0);
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signal mtime_lo : std_ulogic_vector(32 downto 0);
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signal mtime_lo : std_ulogic_vector(31 downto 0);
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signal mtime_lo_msb_ff : std_ulogic;
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signal mtime_lo_nxt : std_ulogic_vector(32 downto 0);
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signal mtime_lo_ovfl : std_ulogic_vector(00 downto 0);
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signal mtime_hi : std_ulogic_vector(31 downto 0);
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signal mtime_hi : std_ulogic_vector(31 downto 0);
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signal inc_hi : std_ulogic_vector(31 downto 0);
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-- irq control --
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-- comparator and IRQ trigger --
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signal cmp_lo : std_ulogic;
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signal cmp_lo : std_ulogic;
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signal cmp_lo_ff : std_ulogic;
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signal cmp_lo_ff : std_ulogic;
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signal cmp_hi : std_ulogic;
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signal cmp_hi : std_ulogic;
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signal cmp_match_ff : std_ulogic;
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signal cmp_match_ff : std_ulogic;
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| Line 112... |
Line 111... |
mtimecmp_hi <= data_i;
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mtimecmp_hi <= data_i;
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end if;
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end if;
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end if;
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end if;
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-- mtime access buffer --
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-- mtime access buffer --
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wdata_buf <= data_i;
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-- wdata_buf <= data_i; -- not required, CPU wdata is stable until transfer is acknowledged
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mtime_lo_we <= wren and bool_to_ulogic_f(boolean(addr = mtime_time_lo_addr_c));
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mtime_lo_we <= wren and bool_to_ulogic_f(boolean(addr = mtime_time_lo_addr_c));
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mtime_hi_we <= wren and bool_to_ulogic_f(boolean(addr = mtime_time_hi_addr_c));
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mtime_hi_we <= wren and bool_to_ulogic_f(boolean(addr = mtime_time_hi_addr_c));
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-- mtime low --
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-- mtime low --
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if (mtime_lo_we = '1') then -- write access
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if (mtime_lo_we = '1') then -- write access
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mtime_lo_msb_ff <= '0';
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mtime_lo <= data_i;
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mtime_lo <= '0' & wdata_buf;
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else -- auto increment
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else -- auto increment
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mtime_lo_msb_ff <= mtime_lo(mtime_lo'left);
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mtime_lo <= mtime_lo_nxt(31 downto 0);
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mtime_lo <= std_ulogic_vector(unsigned(mtime_lo) + 1);
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end if;
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end if;
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mtime_lo_ovfl(0) <= mtime_lo_nxt(32); -- overflow (carry)
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-- mtime high --
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-- mtime high --
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if (mtime_hi_we = '1') then -- write access
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if (mtime_hi_we = '1') then -- write access
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mtime_hi <= wdata_buf;
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mtime_hi <= data_i;
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else -- auto increment (if mtime.low overflows)
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else -- auto increment (if mtime.low overflows)
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mtime_hi <= std_ulogic_vector(unsigned(mtime_hi) + unsigned(inc_hi));
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mtime_hi <= std_ulogic_vector(unsigned(mtime_hi) + unsigned(mtime_lo_ovfl));
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end if;
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end if;
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end if;
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end if;
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end process wr_access;
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end process wr_access;
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-- mtime.time_HI increment (0 or 1) --
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-- mtime.time_LO increment --
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inc_hi(0) <= mtime_lo_msb_ff xor mtime_lo(mtime_lo'left);
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mtime_lo_nxt <= std_ulogic_vector(unsigned('0' & mtime_lo) + 1);
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inc_hi(31 downto 1) <= (others => '0');
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-- Read Access ----------------------------------------------------------------------------
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-- Read Access ----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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rd_access: process(clk_i)
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rd_access: process(clk_i)
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| Line 149... |
Line 146... |
ack_o <= acc_en and (rden_i or wren_i);
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ack_o <= acc_en and (rden_i or wren_i);
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data_o <= (others => '0'); -- default
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data_o <= (others => '0'); -- default
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if (rden_i = '1') and (acc_en = '1') then
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if (rden_i = '1') and (acc_en = '1') then
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case addr is
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case addr is
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when mtime_time_lo_addr_c => -- mtime LOW
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when mtime_time_lo_addr_c => -- mtime LOW
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data_o <= mtime_lo(31 downto 00);
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data_o <= mtime_lo;
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when mtime_time_hi_addr_c => -- mtime HIGH
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when mtime_time_hi_addr_c => -- mtime HIGH
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data_o <= mtime_hi;
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data_o <= mtime_hi;
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when mtime_cmp_lo_addr_c => -- mtimecmp LOW
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when mtime_cmp_lo_addr_c => -- mtimecmp LOW
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data_o <= mtimecmp_lo;
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data_o <= mtimecmp_lo;
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when others => -- mtime_cmp_hi_addr_c -- mtimecmp HIGH
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when others => -- mtime_cmp_hi_addr_c -- mtimecmp HIGH
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| Line 162... |
Line 159... |
end if;
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end if;
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end if;
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end if;
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end process rd_access;
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end process rd_access;
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-- system time output for cpu --
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-- system time output for cpu --
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time_o <= mtime_hi & mtime_lo(31 downto 00);
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time_o <= mtime_hi & mtime_lo;
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-- Comparator -----------------------------------------------------------------------------
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-- Comparator -----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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cmp_sync: process(clk_i)
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cmp_sync: process(clk_i)
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| Line 177... |
Line 174... |
irq_o <= cmp_lo_ff and cmp_hi and (not cmp_match_ff);
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irq_o <= cmp_lo_ff and cmp_hi and (not cmp_match_ff);
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end if;
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end if;
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end process cmp_sync;
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end process cmp_sync;
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-- test words --
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-- test words --
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cmp_lo <= '1' when (unsigned(mtime_lo(31 downto 00)) >= unsigned(mtimecmp_lo)) else '0';
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cmp_lo <= '1' when (unsigned(mtime_lo) >= unsigned(mtimecmp_lo)) else '0';
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cmp_hi <= '1' when (unsigned(mtime_hi(31 downto 00)) >= unsigned(mtimecmp_hi)) else '0';
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cmp_hi <= '1' when (unsigned(mtime_hi) >= unsigned(mtimecmp_hi)) else '0';
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end neorv32_mtime_rtl;
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end neorv32_mtime_rtl;
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