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Line 67... |
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-- access control --
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-- access control --
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signal acc_en : std_ulogic; -- module access enable
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signal acc_en : std_ulogic; -- module access enable
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signal addr : std_ulogic_vector(31 downto 0); -- access address
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signal addr : std_ulogic_vector(31 downto 0); -- access address
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signal wren : std_ulogic; -- module access enable
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signal wren : std_ulogic; -- module access enable
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signal rden : std_ulogic; -- read enable
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-- time write access buffer --
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-- time write access buffer --
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signal mtime_lo_we : std_ulogic;
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signal mtime_lo_we : std_ulogic;
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signal mtime_hi_we : std_ulogic;
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signal mtime_hi_we : std_ulogic;
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Line 94... |
-- Access Control -------------------------------------------------------------------------
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-- Access Control -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = mtime_base_c(hi_abb_c downto lo_abb_c)) else '0';
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = mtime_base_c(hi_abb_c downto lo_abb_c)) else '0';
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addr <= mtime_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
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addr <= mtime_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
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wren <= acc_en and wren_i;
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wren <= acc_en and wren_i;
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rden <= acc_en and rden_i;
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-- Write Access ---------------------------------------------------------------------------
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-- Write Access ---------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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wr_access: process(clk_i)
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wr_access: process(clk_i)
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Line 143... |
-- Read Access ----------------------------------------------------------------------------
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-- Read Access ----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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rd_access: process(clk_i)
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rd_access: process(clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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ack_o <= acc_en and (rden_i or wren_i);
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ack_o <= rden or wren;
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data_o <= (others => '0'); -- default
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data_o <= (others => '0'); -- default
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if (rden_i = '1') and (acc_en = '1') then
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if (rden = '1') then
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case addr is
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case addr(3 downto 2) is
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when mtime_time_lo_addr_c => -- mtime LOW
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when "00" => data_o <= mtime_lo; -- mtime LOW
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data_o <= mtime_lo;
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when "01" => data_o <= mtime_hi; -- mtime HIGH
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when mtime_time_hi_addr_c => -- mtime HIGH
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when "10" => data_o <= mtimecmp_lo; -- mtimecmp LOW
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data_o <= mtime_hi;
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when others => data_o <= mtimecmp_hi; -- mtimecmp HIGH
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when mtime_cmp_lo_addr_c => -- mtimecmp LOW
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data_o <= mtimecmp_lo;
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when others => -- mtime_cmp_hi_addr_c -- mtimecmp HIGH
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data_o <= mtimecmp_hi;
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end process rd_access;
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end process rd_access;
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