| Line 142... |
Line 142... |
-- transmission buffer --
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-- transmission buffer --
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type tx_fifo_t is array (0 to tx_buffer_entries_c-1) of std_ulogic_vector(31+1 downto 0);
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type tx_fifo_t is array (0 to tx_buffer_entries_c-1) of std_ulogic_vector(31+1 downto 0);
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type tx_buffer_t is record
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type tx_buffer_t is record
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we : std_ulogic; -- write enable
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we : std_ulogic; -- write enable
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re : std_ulogic; -- read enable
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re : std_ulogic; -- read enable
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wdata : std_ulogic_vector(31 downto 0); -- write data (excluding excluding)
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wdata : std_ulogic_vector(31 downto 0); -- write data (excluding mode)
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rdata : std_ulogic_vector(31+1 downto 0); -- read data (including mode)
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rdata : std_ulogic_vector(31+1 downto 0); -- read data (including mode)
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--
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--
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w_pnt : std_ulogic_vector(index_size_f(tx_buffer_entries_c) downto 0); -- write pointer
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r_pnt : std_ulogic_vector(index_size_f(tx_buffer_entries_c) downto 0); -- read pointer
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match : std_ulogic;
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empty : std_ulogic;
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empty_ff : std_ulogic;
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full : std_ulogic;
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avail : std_ulogic; -- data available?
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avail : std_ulogic; -- data available?
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free : std_ulogic; -- free entry available?
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free : std_ulogic; -- free entry available?
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free_ff : std_ulogic;
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free_ff : std_ulogic;
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empty : std_ulogic;
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empty_ff : std_ulogic;
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--
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--
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data : tx_fifo_t; -- fifo memory
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data : tx_fifo_t; -- fifo memory
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end record;
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end record;
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signal tx_buffer : tx_buffer_t;
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signal tx_buffer : tx_buffer_t;
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signal fifo_clear : std_ulogic;
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signal fifo_wdata : std_ulogic_vector(31+1 downto 0);
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-- serial transmission engine --
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-- serial transmission engine --
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type serial_state_t is (S_IDLE, S_INIT, S_GETBIT, S_PULSE);
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type serial_state_t is (S_IDLE, S_INIT, S_GETBIT, S_PULSE);
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type serial_t is record
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type serial_t is record
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-- state control --
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-- state control --
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| Line 244... |
Line 242... |
clkgen_en_o <= ctrl.enable;
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clkgen_en_o <= ctrl.enable;
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-- TX Buffer (FIFO) -----------------------------------------------------------------------
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-- TX Buffer (FIFO) -----------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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instr_prefetch_buffer: process(clk_i)
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tx_data_fifo: neorv32_fifo
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begin
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generic map (
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if rising_edge(clk_i) then
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FIFO_DEPTH => tx_buffer_entries_c, -- number of fifo entries; has to be a power of two; min 1
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FIFO_WIDTH => 32+1, -- size of data elements in fifo
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FIFO_RSYNC => true, -- sync read
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FIFO_SAFE => false -- no safe access required (ensured by FIFO-external control)
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)
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port map (
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-- control --
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clk_i => clk_i, -- clock, rising edge
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rstn_i => '1', -- async reset, low-active
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clear_i => fifo_clear, -- sync reset, high-active
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-- write port --
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-- write port --
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if (ctrl.enable = '0') then
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wdata_i => fifo_wdata, -- write data
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tx_buffer.w_pnt <= (others => '0');
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we_i => tx_buffer.we, -- write enable
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elsif (tx_buffer.we = '1') then
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free_o => tx_buffer.free, -- at least one entry is free when set
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tx_buffer.w_pnt <= std_ulogic_vector(unsigned(tx_buffer.w_pnt) + 1);
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end if;
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if (tx_buffer.we = '1') then -- write data
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tx_buffer.data(to_integer(unsigned(tx_buffer.w_pnt(tx_buffer.w_pnt'left-1 downto 0)))) <= ctrl.mode & tx_buffer.wdata;
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end if;
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-- read port --
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-- read port --
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if (ctrl.enable = '0') then
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re_i => tx_buffer.re, -- read enable
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tx_buffer.r_pnt <= (others => '0');
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rdata_o => tx_buffer.rdata, -- read data
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elsif (tx_buffer.re = '1') then
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avail_o => tx_buffer.avail -- data available when set
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tx_buffer.r_pnt <= std_ulogic_vector(unsigned(tx_buffer.r_pnt) + 1);
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);
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end if;
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tx_buffer.rdata <= tx_buffer.data(to_integer(unsigned(tx_buffer.r_pnt(tx_buffer.r_pnt'left-1 downto 0)))); -- sync read
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-- helper signals --
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-- status buffer --
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fifo_clear <= not ctrl.enable;
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tx_buffer.empty_ff <= tx_buffer.empty;
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fifo_wdata <= ctrl.mode & tx_buffer.wdata;
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tx_buffer.free_ff <= tx_buffer.free;
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tx_buffer.empty <= not tx_buffer.avail;
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end if;
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end process instr_prefetch_buffer;
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-- status --
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tx_buffer.match <= '1' when (tx_buffer.r_pnt(tx_buffer.r_pnt'left-1 downto 0) = tx_buffer.w_pnt(tx_buffer.w_pnt'left-1 downto 0)) else '0';
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tx_buffer.full <= '1' when (tx_buffer.r_pnt(tx_buffer.r_pnt'left) /= tx_buffer.w_pnt(tx_buffer.w_pnt'left)) and (tx_buffer.match = '1') else '0';
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tx_buffer.empty <= '1' when (tx_buffer.r_pnt(tx_buffer.r_pnt'left) = tx_buffer.w_pnt(tx_buffer.w_pnt'left)) and (tx_buffer.match = '1') else '0';
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tx_buffer.free <= not tx_buffer.full;
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tx_buffer.avail <= not tx_buffer.empty;
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-- Buffer Status Flag and IRQ Generator ---------------------------------------------------
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-- Buffer Status Flag and IRQ Generator ---------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- ctrl.bscon = 0: clear buffer/busy status flag and send IRQ if -> there is at least one free entry in buffer
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-- ctrl.bscon = 0: clear buffer/busy status flag and send IRQ if -> there is at least one free entry in buffer
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