| Line 47... |
Line 47... |
-- use dedicated hardware reset value for UNCRITICAL CPU registers --
|
-- use dedicated hardware reset value for UNCRITICAL CPU registers --
|
-- FALSE=reset value is irrelevant (might simplify HW), default; TRUE=defined LOW reset value
|
-- FALSE=reset value is irrelevant (might simplify HW), default; TRUE=defined LOW reset value
|
constant dedicated_reset_c : boolean := false;
|
constant dedicated_reset_c : boolean := false;
|
|
|
-- "critical" number of implemented PMP regions --
|
-- "critical" number of implemented PMP regions --
|
-- if more PMP regions (> pmp_num_regions_critical_c) are defined, another register stage is automatically inserted into the memory interfaces
|
-- if more PMP regions (> pmp_num_regions_critical_c) are defined, another register stage is automatically inserted into
|
-- increasing instruction fetch & data access latency by +1 cycle but also reducing critical path length
|
-- the memory interfaces increasing instruction fetch & data access latency by +1 cycle but also reducing critical path length
|
constant pmp_num_regions_critical_c : natural := 8; -- default=8
|
constant pmp_num_regions_critical_c : natural := 8; -- default=8
|
|
|
-- "response time window" for processor-internal modules --
|
-- "response time window" for processor-internal modules --
|
-- = cycles after which an *unacknowledged* internal bus access will timeout and trigger a bus fault exception (min 2)
|
-- = cycles after which an *unacknowledged* internal bus access will timeout and trigger a bus fault exception (min 2)
|
constant max_proc_int_response_time_c : natural := 15;
|
constant max_proc_int_response_time_c : natural := 15;
|
| Line 63... |
Line 63... |
constant jtag_tap_idcode_manid_c : std_ulogic_vector(10 downto 0) := "00000000000"; -- manufacturer id
|
constant jtag_tap_idcode_manid_c : std_ulogic_vector(10 downto 0) := "00000000000"; -- manufacturer id
|
|
|
-- Architecture Constants (do not modify!) ------------------------------------------------
|
-- Architecture Constants (do not modify!) ------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant data_width_c : natural := 32; -- native data path width - do not change!
|
constant data_width_c : natural := 32; -- native data path width - do not change!
|
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01060900"; -- no touchy!
|
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01070000"; -- NEORV32 version - no touchy!
|
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
|
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
|
|
|
-- Check if we're inside the Matrix -------------------------------------------------------
|
-- Check if we're inside the Matrix -------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant is_simulation_c : boolean := false -- seems like we're on real hardware
|
constant is_simulation_c : boolean := false -- seems like we're on real hardware
|
| Line 345... |
Line 345... |
constant ctrl_alu_op1_c : natural := 19; -- ALU operation select bit 1
|
constant ctrl_alu_op1_c : natural := 19; -- ALU operation select bit 1
|
constant ctrl_alu_op2_c : natural := 20; -- ALU operation select bit 2
|
constant ctrl_alu_op2_c : natural := 20; -- ALU operation select bit 2
|
constant ctrl_alu_opa_mux_c : natural := 21; -- operand A select (0=rs1, 1=PC)
|
constant ctrl_alu_opa_mux_c : natural := 21; -- operand A select (0=rs1, 1=PC)
|
constant ctrl_alu_opb_mux_c : natural := 22; -- operand B select (0=rs2, 1=IMM)
|
constant ctrl_alu_opb_mux_c : natural := 22; -- operand B select (0=rs2, 1=IMM)
|
constant ctrl_alu_unsigned_c : natural := 23; -- is unsigned ALU operation
|
constant ctrl_alu_unsigned_c : natural := 23; -- is unsigned ALU operation
|
constant ctrl_alu_shift_dir_c : natural := 24; -- shift direction (0=left, 1=right)
|
constant ctrl_alu_frm0_c : natural := 24; -- FPU rounding mode bit 0
|
constant ctrl_alu_shift_ar_c : natural := 25; -- is arithmetic shift
|
constant ctrl_alu_frm1_c : natural := 25; -- FPU rounding mode bit 1
|
constant ctrl_alu_frm0_c : natural := 26; -- FPU rounding mode bit 0
|
constant ctrl_alu_frm2_c : natural := 26; -- FPU rounding mode bit 2
|
constant ctrl_alu_frm1_c : natural := 27; -- FPU rounding mode bit 1
|
|
constant ctrl_alu_frm2_c : natural := 28; -- FPU rounding mode bit 2
|
|
-- bus interface --
|
-- bus interface --
|
constant ctrl_bus_size_lsb_c : natural := 29; -- transfer size lsb (00=byte, 01=half-word)
|
constant ctrl_bus_size_lsb_c : natural := 27; -- transfer size lsb (00=byte, 01=half-word)
|
constant ctrl_bus_size_msb_c : natural := 30; -- transfer size msb (10=word, 11=?)
|
constant ctrl_bus_size_msb_c : natural := 28; -- transfer size msb (10=word, 11=?)
|
constant ctrl_bus_rd_c : natural := 31; -- read data request
|
constant ctrl_bus_rd_c : natural := 29; -- read data request
|
constant ctrl_bus_wr_c : natural := 32; -- write data request
|
constant ctrl_bus_wr_c : natural := 30; -- write data request
|
constant ctrl_bus_if_c : natural := 33; -- instruction fetch request
|
constant ctrl_bus_if_c : natural := 31; -- instruction fetch request
|
constant ctrl_bus_mo_we_c : natural := 34; -- memory address and data output register write enable
|
constant ctrl_bus_mo_we_c : natural := 32; -- memory address and data output register write enable
|
constant ctrl_bus_mi_we_c : natural := 35; -- memory data input register write enable
|
constant ctrl_bus_mi_we_c : natural := 33; -- memory data input register write enable
|
constant ctrl_bus_unsigned_c : natural := 36; -- is unsigned load
|
constant ctrl_bus_unsigned_c : natural := 34; -- is unsigned load
|
constant ctrl_bus_fence_c : natural := 37; -- executed fence operation
|
constant ctrl_bus_fence_c : natural := 35; -- executed fence operation
|
constant ctrl_bus_fencei_c : natural := 38; -- executed fencei operation
|
constant ctrl_bus_fencei_c : natural := 36; -- executed fencei operation
|
constant ctrl_bus_lock_c : natural := 39; -- make atomic/exclusive access lock
|
constant ctrl_bus_lock_c : natural := 37; -- make atomic/exclusive access lock
|
constant ctrl_bus_de_lock_c : natural := 40; -- remove atomic/exclusive access
|
constant ctrl_bus_de_lock_c : natural := 38; -- remove atomic/exclusive access
|
constant ctrl_bus_ch_lock_c : natural := 41; -- evaluate atomic/exclusive lock (SC operation)
|
constant ctrl_bus_ch_lock_c : natural := 39; -- evaluate atomic/exclusive lock (SC operation)
|
-- alu co-processors --
|
-- alu co-processors --
|
constant ctrl_cp_id_lsb_c : natural := 42; -- cp select ID lsb [ALIAS]
|
constant ctrl_cp_trig0_c : natural := 40; -- trigger CP0
|
constant ctrl_cp_trig0_c : natural := 42; -- trigger CP0
|
constant ctrl_cp_trig1_c : natural := 41; -- trigger CP1
|
constant ctrl_cp_trig1_c : natural := 43; -- trigger CP1
|
constant ctrl_cp_trig2_c : natural := 42; -- trigger CP2
|
constant ctrl_cp_trig2_c : natural := 44; -- trigger CP2
|
constant ctrl_cp_trig3_c : natural := 43; -- trigger CP3
|
constant ctrl_cp_trig3_c : natural := 45; -- trigger CP3
|
constant ctrl_cp_trig4_c : natural := 44; -- trigger CP4
|
constant ctrl_cp_trig4_c : natural := 46; -- trigger CP4
|
constant ctrl_cp_trig5_c : natural := 45; -- trigger CP5
|
constant ctrl_cp_trig5_c : natural := 47; -- trigger CP5
|
constant ctrl_cp_trig6_c : natural := 46; -- trigger CP6
|
constant ctrl_cp_trig6_c : natural := 48; -- trigger CP6
|
constant ctrl_cp_trig7_c : natural := 47; -- trigger CP7
|
constant ctrl_cp_trig7_c : natural := 49; -- trigger CP7
|
|
constant ctrl_cp_id_msb_c : natural := 49; -- cp select ID msb [ALIAS]
|
|
-- instruction word control blocks (used by cpu co-processors) --
|
-- instruction word control blocks (used by cpu co-processors) --
|
constant ctrl_ir_funct3_0_c : natural := 50; -- funct3 bit 0
|
constant ctrl_ir_funct3_0_c : natural := 48; -- funct3 bit 0
|
constant ctrl_ir_funct3_1_c : natural := 51; -- funct3 bit 1
|
constant ctrl_ir_funct3_1_c : natural := 49; -- funct3 bit 1
|
constant ctrl_ir_funct3_2_c : natural := 52; -- funct3 bit 2
|
constant ctrl_ir_funct3_2_c : natural := 50; -- funct3 bit 2
|
constant ctrl_ir_funct12_0_c : natural := 53; -- funct12 bit 0
|
constant ctrl_ir_funct12_0_c : natural := 51; -- funct12 bit 0
|
constant ctrl_ir_funct12_1_c : natural := 54; -- funct12 bit 1
|
constant ctrl_ir_funct12_1_c : natural := 52; -- funct12 bit 1
|
constant ctrl_ir_funct12_2_c : natural := 55; -- funct12 bit 2
|
constant ctrl_ir_funct12_2_c : natural := 53; -- funct12 bit 2
|
constant ctrl_ir_funct12_3_c : natural := 56; -- funct12 bit 3
|
constant ctrl_ir_funct12_3_c : natural := 54; -- funct12 bit 3
|
constant ctrl_ir_funct12_4_c : natural := 57; -- funct12 bit 4
|
constant ctrl_ir_funct12_4_c : natural := 55; -- funct12 bit 4
|
constant ctrl_ir_funct12_5_c : natural := 58; -- funct12 bit 5
|
constant ctrl_ir_funct12_5_c : natural := 56; -- funct12 bit 5
|
constant ctrl_ir_funct12_6_c : natural := 59; -- funct12 bit 6
|
constant ctrl_ir_funct12_6_c : natural := 57; -- funct12 bit 6
|
constant ctrl_ir_funct12_7_c : natural := 60; -- funct12 bit 7
|
constant ctrl_ir_funct12_7_c : natural := 58; -- funct12 bit 7
|
constant ctrl_ir_funct12_8_c : natural := 61; -- funct12 bit 8
|
constant ctrl_ir_funct12_8_c : natural := 59; -- funct12 bit 8
|
constant ctrl_ir_funct12_9_c : natural := 62; -- funct12 bit 9
|
constant ctrl_ir_funct12_9_c : natural := 60; -- funct12 bit 9
|
constant ctrl_ir_funct12_10_c : natural := 63; -- funct12 bit 10
|
constant ctrl_ir_funct12_10_c : natural := 61; -- funct12 bit 10
|
constant ctrl_ir_funct12_11_c : natural := 64; -- funct12 bit 11
|
constant ctrl_ir_funct12_11_c : natural := 62; -- funct12 bit 11
|
constant ctrl_ir_opcode7_0_c : natural := 65; -- opcode7 bit 0
|
constant ctrl_ir_opcode7_0_c : natural := 63; -- opcode7 bit 0
|
constant ctrl_ir_opcode7_1_c : natural := 66; -- opcode7 bit 1
|
constant ctrl_ir_opcode7_1_c : natural := 64; -- opcode7 bit 1
|
constant ctrl_ir_opcode7_2_c : natural := 67; -- opcode7 bit 2
|
constant ctrl_ir_opcode7_2_c : natural := 65; -- opcode7 bit 2
|
constant ctrl_ir_opcode7_3_c : natural := 68; -- opcode7 bit 3
|
constant ctrl_ir_opcode7_3_c : natural := 66; -- opcode7 bit 3
|
constant ctrl_ir_opcode7_4_c : natural := 69; -- opcode7 bit 4
|
constant ctrl_ir_opcode7_4_c : natural := 67; -- opcode7 bit 4
|
constant ctrl_ir_opcode7_5_c : natural := 70; -- opcode7 bit 5
|
constant ctrl_ir_opcode7_5_c : natural := 68; -- opcode7 bit 5
|
constant ctrl_ir_opcode7_6_c : natural := 71; -- opcode7 bit 6
|
constant ctrl_ir_opcode7_6_c : natural := 69; -- opcode7 bit 6
|
-- cpu status --
|
-- cpu status --
|
constant ctrl_priv_mode_c : natural := 72; -- effective privilege mode
|
constant ctrl_priv_mode_c : natural := 70; -- effective privilege mode
|
constant ctrl_sleep_c : natural := 73; -- set when CPU is in sleep mode
|
constant ctrl_sleep_c : natural := 71; -- set when CPU is in sleep mode
|
constant ctrl_trap_c : natural := 74; -- set when CPU is entering trap execution
|
constant ctrl_trap_c : natural := 72; -- set when CPU is entering trap execution
|
constant ctrl_debug_running_c : natural := 75; -- set when CPU is in debug mode
|
constant ctrl_debug_running_c : natural := 73; -- set when CPU is in debug mode
|
-- control bus size --
|
-- control bus size --
|
constant ctrl_width_c : natural := 76; -- control bus size
|
constant ctrl_width_c : natural := 74; -- control bus size
|
|
|
-- Comparator Bus -------------------------------------------------------------------------
|
-- Comparator Bus -------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant cmp_equal_c : natural := 0;
|
constant cmp_equal_c : natural := 0;
|
constant cmp_less_c : natural := 1; -- for signed and unsigned comparisons
|
constant cmp_less_c : natural := 1; -- for signed and unsigned comparisons
|
| Line 431... |
Line 427... |
constant instr_funct12_msb_c : natural := 31; -- funct12 bit 11
|
constant instr_funct12_msb_c : natural := 31; -- funct12 bit 11
|
constant instr_imm12_lsb_c : natural := 20; -- immediate12 bit 0
|
constant instr_imm12_lsb_c : natural := 20; -- immediate12 bit 0
|
constant instr_imm12_msb_c : natural := 31; -- immediate12 bit 11
|
constant instr_imm12_msb_c : natural := 31; -- immediate12 bit 11
|
constant instr_imm20_lsb_c : natural := 12; -- immediate20 bit 0
|
constant instr_imm20_lsb_c : natural := 12; -- immediate20 bit 0
|
constant instr_imm20_msb_c : natural := 31; -- immediate20 bit 21
|
constant instr_imm20_msb_c : natural := 31; -- immediate20 bit 21
|
constant instr_csr_id_lsb_c : natural := 20; -- csr select bit 0
|
|
constant instr_csr_id_msb_c : natural := 31; -- csr select bit 11
|
|
constant instr_funct5_lsb_c : natural := 27; -- funct5 select bit 0
|
constant instr_funct5_lsb_c : natural := 27; -- funct5 select bit 0
|
constant instr_funct5_msb_c : natural := 31; -- funct5 select bit 4
|
constant instr_funct5_msb_c : natural := 31; -- funct5 select bit 4
|
|
|
-- RISC-V Opcodes -------------------------------------------------------------------------
|
-- RISC-V Opcodes -------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
| Line 452... |
Line 446... |
-- memory access --
|
-- memory access --
|
constant opcode_load_c : std_ulogic_vector(6 downto 0) := "0000011"; -- load (data type via funct3)
|
constant opcode_load_c : std_ulogic_vector(6 downto 0) := "0000011"; -- load (data type via funct3)
|
constant opcode_store_c : std_ulogic_vector(6 downto 0) := "0100011"; -- store (data type via funct3)
|
constant opcode_store_c : std_ulogic_vector(6 downto 0) := "0100011"; -- store (data type via funct3)
|
-- system/csr --
|
-- system/csr --
|
constant opcode_fence_c : std_ulogic_vector(6 downto 0) := "0001111"; -- fence / fence.i
|
constant opcode_fence_c : std_ulogic_vector(6 downto 0) := "0001111"; -- fence / fence.i
|
constant opcode_syscsr_c : std_ulogic_vector(6 downto 0) := "1110011"; -- system/csr access (type via funct3)
|
constant opcode_system_c : std_ulogic_vector(6 downto 0) := "1110011"; -- system/csr access (type via funct3)
|
-- atomic memory access (A) --
|
-- atomic memory access (A) --
|
constant opcode_atomic_c : std_ulogic_vector(6 downto 0) := "0101111"; -- atomic operations (A extension)
|
constant opcode_atomic_c : std_ulogic_vector(6 downto 0) := "0101111"; -- atomic operations (A extension)
|
-- floating point operations (Zfinx-only) (F/D/H/Q) --
|
-- floating point operations (Zfinx-only) (F/D/H/Q) --
|
constant opcode_fop_c : std_ulogic_vector(6 downto 0) := "1010011"; -- dual/single operand instruction
|
constant opcode_fop_c : std_ulogic_vector(6 downto 0) := "1010011"; -- dual/single operand instruction
|
-- official "custom0/1" RISC-V opcodes - free for custom instructions --
|
-- official "custom0/1" RISC-V opcodes - free for custom instructions --
|
| Line 505... |
Line 499... |
-- RISC-V Funct12 -------------------------------------------------------------------------
|
-- RISC-V Funct12 -------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- system --
|
-- system --
|
constant funct12_ecall_c : std_ulogic_vector(11 downto 0) := x"000"; -- ecall
|
constant funct12_ecall_c : std_ulogic_vector(11 downto 0) := x"000"; -- ecall
|
constant funct12_ebreak_c : std_ulogic_vector(11 downto 0) := x"001"; -- ebreak
|
constant funct12_ebreak_c : std_ulogic_vector(11 downto 0) := x"001"; -- ebreak
|
constant funct12_mret_c : std_ulogic_vector(11 downto 0) := x"302"; -- mret
|
|
constant funct12_wfi_c : std_ulogic_vector(11 downto 0) := x"105"; -- wfi
|
constant funct12_wfi_c : std_ulogic_vector(11 downto 0) := x"105"; -- wfi
|
|
constant funct12_mret_c : std_ulogic_vector(11 downto 0) := x"302"; -- mret
|
constant funct12_dret_c : std_ulogic_vector(11 downto 0) := x"7b2"; -- dret
|
constant funct12_dret_c : std_ulogic_vector(11 downto 0) := x"7b2"; -- dret
|
|
|
-- RISC-V Funct5 --------------------------------------------------------------------------
|
-- RISC-V Funct5 --------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- atomic operations --
|
-- atomic operations --
|
| Line 552... |
Line 546... |
constant fp_single_pos_zero_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- positive zero
|
constant fp_single_pos_zero_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- positive zero
|
constant fp_single_neg_zero_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- negative zero
|
constant fp_single_neg_zero_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- negative zero
|
|
|
-- RISC-V CSR Addresses -------------------------------------------------------------------
|
-- RISC-V CSR Addresses -------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
|
constant csr_zero_c : std_ulogic_vector(11 downto 0) := x"000"; -- always returns zero, only relevant for hardware access
|
-- <<< standard read/write CSRs >>> --
|
-- <<< standard read/write CSRs >>> --
|
-- user floating-point CSRs --
|
-- user floating-point CSRs --
|
constant csr_class_float_c : std_ulogic_vector(09 downto 0) := x"00" & "00"; -- floating point
|
constant csr_class_float_c : std_ulogic_vector(09 downto 0) := x"00" & "00"; -- floating point
|
constant csr_fflags_c : std_ulogic_vector(11 downto 0) := x"001";
|
constant csr_fflags_c : std_ulogic_vector(11 downto 0) := x"001";
|
constant csr_frm_c : std_ulogic_vector(11 downto 0) := x"002";
|
constant csr_frm_c : std_ulogic_vector(11 downto 0) := x"002";
|
| Line 845... |
Line 840... |
--constant trap_henv_c x : std_ulogic_vector(6 downto 0) := "0" & "0" & "01010"; -- 0.10: environment call from h-mode
|
--constant trap_henv_c x : std_ulogic_vector(6 downto 0) := "0" & "0" & "01010"; -- 0.10: environment call from h-mode
|
constant trap_menv_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "01011"; -- 0.11: environment call from m-mode
|
constant trap_menv_c : std_ulogic_vector(6 downto 0) := "0" & "0" & "01011"; -- 0.11: environment call from m-mode
|
--constant trap_ipf_c x : std_ulogic_vector(6 downto 0) := "0" & "0" & "01100"; -- 0.12: instruction page fault
|
--constant trap_ipf_c x : std_ulogic_vector(6 downto 0) := "0" & "0" & "01100"; -- 0.12: instruction page fault
|
--constant trap_lpf_c x : std_ulogic_vector(6 downto 0) := "0" & "0" & "01101"; -- 0.13: load page fault
|
--constant trap_lpf_c x : std_ulogic_vector(6 downto 0) := "0" & "0" & "01101"; -- 0.13: load page fault
|
--constant trap_???_c x : std_ulogic_vector(6 downto 0) := "0" & "0" & "01110"; -- 0.14: reserved
|
--constant trap_???_c x : std_ulogic_vector(6 downto 0) := "0" & "0" & "01110"; -- 0.14: reserved
|
--constant trap_lpf_c x : std_ulogic_vector(6 downto 0) := "0" & "0" & "01111"; -- 0.15: store page fault
|
--constant trap_spf_c x : std_ulogic_vector(6 downto 0) := "0" & "0" & "01111"; -- 0.15: store page fault
|
-- NEORV32-specific (custom) synchronous exceptions --
|
-- NEORV32-specific (custom) synchronous exceptions --
|
-- none implemented yet
|
-- none implemented yet
|
-- RISC-V compliant asynchronous exceptions (interrupts) --
|
-- RISC-V compliant asynchronous exceptions (interrupts) --
|
constant trap_msi_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "00011"; -- 1.3: machine software interrupt
|
constant trap_msi_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "00011"; -- 1.3: machine software interrupt
|
constant trap_mti_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "00111"; -- 1.7: machine timer interrupt
|
constant trap_mti_c : std_ulogic_vector(6 downto 0) := "1" & "0" & "00111"; -- 1.7: machine timer interrupt
|
