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package neorv32_package is
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package neorv32_package is
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-- Architecture Constants -----------------------------------------------------------------
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-- Architecture Constants -----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant data_width_c : natural := 32; -- data width - FIXED!
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constant data_width_c : natural := 32; -- data width - FIXED!
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01000100"; -- no touchy!
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01000600"; -- no touchy!
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-- Internal Functions ---------------------------------------------------------------------
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-- Internal Functions ---------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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function index_size_f(input : natural) return natural;
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function index_size_f(input : natural) return natural;
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function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural;
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function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural;
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constant ctrl_bus_if_c : natural := 35; -- instruction fetch request (1: output PC, 0: output MAR)
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constant ctrl_bus_if_c : natural := 35; -- instruction fetch request (1: output PC, 0: output MAR)
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constant ctrl_bus_mar_we_c : natural := 36; -- memory address register write enable
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constant ctrl_bus_mar_we_c : natural := 36; -- memory address register write enable
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constant ctrl_bus_mdo_we_c : natural := 37; -- memory data out register write enable
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constant ctrl_bus_mdo_we_c : natural := 37; -- memory data out register write enable
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constant ctrl_bus_mdi_we_c : natural := 38; -- memory data in register write enable
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constant ctrl_bus_mdi_we_c : natural := 38; -- memory data in register write enable
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constant ctrl_bus_unsigned_c : natural := 39; -- is unsigned load
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constant ctrl_bus_unsigned_c : natural := 39; -- is unsigned load
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constant ctrl_bus_exc_ack_c : natural := 40; -- acknowledge bus exception
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constant ctrl_bus_reset_c : natural := 41; -- reset bus unit, terminate all actions
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-- co-processor --
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-- co-processor --
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constant ctrl_cp_use_c : natural := 40; -- is cp operation
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constant ctrl_cp_use_c : natural := 42; -- is cp operation
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constant ctrl_cp_id_lsb_c : natural := 41; -- cp select lsb
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constant ctrl_cp_id_lsb_c : natural := 43; -- cp select lsb
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constant ctrl_cp_id_msb_c : natural := 42; -- cp select msb
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constant ctrl_cp_id_msb_c : natural := 44; -- cp select msb
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constant ctrl_cp_cmd0_c : natural := 43; -- cp command bit 0
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constant ctrl_cp_cmd0_c : natural := 45; -- cp command bit 0
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constant ctrl_cp_cmd1_c : natural := 44; -- cp command bit 1
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constant ctrl_cp_cmd1_c : natural := 46; -- cp command bit 1
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constant ctrl_cp_cmd2_c : natural := 45; -- cp command bit 2
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constant ctrl_cp_cmd2_c : natural := 47; -- cp command bit 2
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-- system --
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constant ctrl_sys_c_ext_en_c : natural := 46; -- CPU C extension enabled
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constant ctrl_sys_m_ext_en_c : natural := 47; -- CPU M extension enabled
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-- control bus size --
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-- control bus size --
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constant ctrl_width_c : natural := 48; -- control bus size
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constant ctrl_width_c : natural := 48; -- control bus size
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-- ALU Comparator Bus ---------------------------------------------------------------------
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-- ALU Comparator Bus ---------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant funct3_csrrci_c : std_ulogic_vector(2 downto 0) := "111"; -- atomic read & clear bit immediate
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constant funct3_csrrci_c : std_ulogic_vector(2 downto 0) := "111"; -- atomic read & clear bit immediate
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-- fence --
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-- fence --
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constant funct3_fence_c : std_ulogic_vector(2 downto 0) := "000"; -- fence - order IO/memory access (->NOP)
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constant funct3_fence_c : std_ulogic_vector(2 downto 0) := "000"; -- fence - order IO/memory access (->NOP)
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constant funct3_fencei_c : std_ulogic_vector(2 downto 0) := "001"; -- fencei - instructon stream sync
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constant funct3_fencei_c : std_ulogic_vector(2 downto 0) := "001"; -- fencei - instructon stream sync
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-- RISC-V Funct12 --------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- system --
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constant funct12_ecall_c : std_ulogic_vector(11 downto 0) := x"000"; -- ECALL
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constant funct12_ebreak_c : std_ulogic_vector(11 downto 0) := x"001"; -- EBREAK
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constant funct12_mret_c : std_ulogic_vector(11 downto 0) := x"302"; -- MRET
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constant funct12_wfi_c : std_ulogic_vector(11 downto 0) := x"105"; -- WFI
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-- Co-Processor Operations ----------------------------------------------------------------
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-- Co-Processor Operations ----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- cp ids --
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-- cp ids --
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constant cp_sel_muldiv_c : std_ulogic_vector(1 downto 0) := "00"; -- MULDIV CP
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constant cp_sel_muldiv_c : std_ulogic_vector(1 downto 0) := "00"; -- MULDIV CP
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-- muldiv cp --
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-- muldiv cp --
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bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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bus_we_o : out std_ulogic; -- write enable
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bus_we_o : out std_ulogic; -- write enable
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bus_re_o : out std_ulogic; -- read enable
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bus_re_o : out std_ulogic; -- read enable
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bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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bus_err_i : in std_ulogic; -- bus transfer error
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bus_err_i : in std_ulogic; -- bus transfer error
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-- system time input from MTIME --
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time_i : in std_ulogic_vector(63 downto 0); -- current system time
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-- external interrupts --
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-- external interrupts --
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clic_irq_i : in std_ulogic; -- CLIC interrupt request
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clic_irq_i : in std_ulogic; -- CLIC interrupt request
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mtime_irq_i : in std_ulogic -- machine timer interrupt
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mtime_irq_i : in std_ulogic -- machine timer interrupt
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);
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);
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end component;
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end component;
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csr_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR write data
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csr_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR write data
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csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
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csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
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-- external interrupt --
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-- external interrupt --
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clic_irq_i : in std_ulogic; -- CLIC interrupt request
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clic_irq_i : in std_ulogic; -- CLIC interrupt request
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mtime_irq_i : in std_ulogic; -- machine timer interrupt
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mtime_irq_i : in std_ulogic; -- machine timer interrupt
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-- system time input from MTIME --
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time_i : in std_ulogic_vector(63 downto 0); -- current system time
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-- bus access exceptions --
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-- bus access exceptions --
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mar_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory address register
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mar_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory address register
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ma_instr_i : in std_ulogic; -- misaligned instruction address
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ma_instr_i : in std_ulogic; -- misaligned instruction address
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ma_load_i : in std_ulogic; -- misaligned load data address
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ma_load_i : in std_ulogic; -- misaligned load data address
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ma_store_i : in std_ulogic; -- misaligned store data address
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ma_store_i : in std_ulogic; -- misaligned store data address
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be_instr_i : in std_ulogic; -- bus error on instruction access
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be_instr_i : in std_ulogic; -- bus error on instruction access
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be_load_i : in std_ulogic; -- bus error on load data access
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be_load_i : in std_ulogic; -- bus error on load data access
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be_store_i : in std_ulogic; -- bus error on store data access
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be_store_i : in std_ulogic; -- bus error on store data access
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bus_exc_ack_o : out std_ulogic; -- bus exception error acknowledge
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bus_busy_i : in std_ulogic -- bus unit is busy
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bus_busy_i : in std_ulogic -- bus unit is busy
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);
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);
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end component;
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end component;
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-- Component: CPU Register File -----------------------------------------------------------
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-- Component: CPU Register File -----------------------------------------------------------
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end component;
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end component;
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-- Component: CPU ALU ---------------------------------------------------------------------
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-- Component: CPU ALU ---------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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component neorv32_cpu_alu
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component neorv32_cpu_alu
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generic (
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CPU_EXTENSION_RISCV_M : boolean := true -- implement muld/div extension?
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);
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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rstn_i : in std_ulogic; -- global reset, low-active, async
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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-- Component: CPU Bus Interface -----------------------------------------------------------
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-- Component: CPU Bus Interface -----------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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component neorv32_cpu_bus
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component neorv32_cpu_bus
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generic (
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generic (
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CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
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MEM_EXT_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
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MEM_EXT_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
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);
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);
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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be_instr_o : out std_ulogic; -- bus error on instruction access
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be_instr_o : out std_ulogic; -- bus error on instruction access
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be_load_o : out std_ulogic; -- bus error on load data access
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be_load_o : out std_ulogic; -- bus error on load data access
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be_store_o : out std_ulogic; -- bus error on store data
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be_store_o : out std_ulogic; -- bus error on store data
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bus_wait_o : out std_ulogic; -- wait for bus operation to finish
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bus_wait_o : out std_ulogic; -- wait for bus operation to finish
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bus_busy_o : out std_ulogic; -- bus unit is busy
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bus_busy_o : out std_ulogic; -- bus unit is busy
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exc_ack_i : in std_ulogic; -- exception controller ACK
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-- bus system --
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-- bus system --
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bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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bus_we_o : out std_ulogic; -- write enable
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bus_we_o : out std_ulogic; -- write enable
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bus_re_o : out std_ulogic; -- read enable
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bus_re_o : out std_ulogic; -- read enable
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bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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bus_err_i : in std_ulogic -- bus transfer error
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bus_err_i : in std_ulogic -- bus transfer error
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);
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);
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end component;
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end component;
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wren_i : in std_ulogic; -- write enable
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wren_i : in std_ulogic; -- write enable
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ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
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ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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ack_o : out std_ulogic; -- transfer acknowledge
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ack_o : out std_ulogic; -- transfer acknowledge
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-- time output for CPU --
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time_o : out std_ulogic_vector(63 downto 0); -- current system time
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-- interrupt --
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-- interrupt --
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irq_o : out std_ulogic -- interrupt request
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irq_o : out std_ulogic -- interrupt request
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);
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);
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end component;
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end component;
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rden_i : in std_ulogic; -- read enable
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rden_i : in std_ulogic; -- read enable
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wren_i : in std_ulogic; -- write enable
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wren_i : in std_ulogic; -- write enable
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ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
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ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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cancel_i : in std_ulogic; -- cancel current bus transaction
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ack_o : out std_ulogic; -- transfer acknowledge
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ack_o : out std_ulogic; -- transfer acknowledge
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err_o : out std_ulogic; -- transfer error
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err_o : out std_ulogic; -- transfer error
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-- wishbone interface --
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-- wishbone interface --
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wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
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wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
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wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data
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wb_dat_i : in std_ulogic_vector(31 downto 0); -- read data
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