| Line 39... |
Line 39... |
package neorv32_package is
|
package neorv32_package is
|
|
|
-- Architecture Constants -----------------------------------------------------------------
|
-- Architecture Constants -----------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant data_width_c : natural := 32; -- data width - FIXED!
|
constant data_width_c : natural := 32; -- data width - FIXED!
|
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01000600"; -- no touchy!
|
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01020005"; -- no touchy!
|
|
|
-- Internal Functions ---------------------------------------------------------------------
|
-- Helper Functions -----------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
function index_size_f(input : natural) return natural;
|
function index_size_f(input : natural) return natural;
|
function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural;
|
function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural;
|
function cond_sel_stdulogicvector_f(cond : boolean; val_t : std_ulogic_vector; val_f : std_ulogic_vector) return std_ulogic_vector;
|
function cond_sel_stdulogicvector_f(cond : boolean; val_t : std_ulogic_vector; val_f : std_ulogic_vector) return std_ulogic_vector;
|
function bool_to_ulogic_f(cond : boolean) return std_ulogic;
|
function bool_to_ulogic_f(cond : boolean) return std_ulogic;
|
| Line 122... |
Line 122... |
constant trng_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0"; -- base address, fixed!
|
constant trng_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC0"; -- base address, fixed!
|
constant trng_size_c : natural := 2*4; -- bytes, fixed!
|
constant trng_size_c : natural := 2*4; -- bytes, fixed!
|
constant trng_ctrl_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(trng_base_c) + x"00000000");
|
constant trng_ctrl_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(trng_base_c) + x"00000000");
|
constant trng_data_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(trng_base_c) + x"00000004");
|
constant trng_data_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(trng_base_c) + x"00000004");
|
|
|
-- RESERVED --
|
-- Dummy Device (with SIMULATION output) (DEVNULL) --
|
--constant ???_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC8"; -- base address, fixed!
|
constant devnull_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFC8"; -- base address, fixed!
|
--constant ???_size_c : natural := 13*4; -- bytes, fixed!
|
|
|
|
-- Dummy Device (with SIM output) (DEVNULL) --
|
|
constant devnull_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFFC"; -- base address, fixed!
|
|
constant devnull_size_c : natural := 1*4; -- bytes, fixed!
|
constant devnull_size_c : natural := 1*4; -- bytes, fixed!
|
constant devnull_data_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(devnull_base_c) + x"00000000");
|
constant devnull_data_addr_c : std_ulogic_vector(31 downto 0) := std_ulogic_vector(unsigned(devnull_base_c) + x"00000000");
|
|
|
|
-- RESERVED --
|
|
--constant ???_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFCC"; -- base address, fixed!
|
|
--constant ???_size_c : natural := 5*4; -- bytes, fixed!
|
|
|
|
-- System Information Memory (with SIMULATION output) (SYSINFO) --
|
|
constant sysinfo_base_c : std_ulogic_vector(data_width_c-1 downto 0) := x"FFFFFFE0"; -- base address, fixed!
|
|
constant sysinfo_size_c : natural := 8*4; -- bytes, fixed!
|
|
|
-- Main Control Bus -----------------------------------------------------------------------
|
-- Main Control Bus -----------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- register file --
|
-- register file --
|
constant ctrl_rf_in_mux_lsb_c : natural := 0; -- input source select lsb (00=ALU, 01=MEM)
|
constant ctrl_rf_in_mux_lsb_c : natural := 0; -- input source select lsb (00=ALU, 01=MEM)
|
constant ctrl_rf_in_mux_msb_c : natural := 1; -- input source select msb (10=PC, 11=CSR)
|
constant ctrl_rf_in_mux_msb_c : natural := 1; -- input source select msb (10=PC, 11=CSR)
|
| Line 159... |
Line 163... |
-- alu --
|
-- alu --
|
constant ctrl_alu_cmd0_c : natural := 20; -- ALU command bit 0
|
constant ctrl_alu_cmd0_c : natural := 20; -- ALU command bit 0
|
constant ctrl_alu_cmd1_c : natural := 21; -- ALU command bit 1
|
constant ctrl_alu_cmd1_c : natural := 21; -- ALU command bit 1
|
constant ctrl_alu_cmd2_c : natural := 22; -- ALU command bit 2
|
constant ctrl_alu_cmd2_c : natural := 22; -- ALU command bit 2
|
constant ctrl_alu_opa_mux_lsb_c : natural := 23; -- operand A select lsb (00=rs1, 01=PC)
|
constant ctrl_alu_opa_mux_lsb_c : natural := 23; -- operand A select lsb (00=rs1, 01=PC)
|
constant ctrl_alu_opa_mux_msb_c : natural := 24; -- operand A select msb (10=CSR, 11=?)
|
constant ctrl_alu_opa_mux_msb_c : natural := 24; -- operand A select msb (1-=CSR)
|
constant ctrl_alu_opb_mux_lsb_c : natural := 25; -- operand B select lsb (00=rs2, 01=IMM)
|
constant ctrl_alu_opb_mux_lsb_c : natural := 25; -- operand B select lsb (00=rs2, 01=IMM)
|
constant ctrl_alu_opb_mux_msb_c : natural := 26; -- operand B select msb (10=rs1, 11=?)
|
constant ctrl_alu_opb_mux_msb_c : natural := 26; -- operand B select msb (1-=rs1)
|
constant ctrl_alu_opc_mux_c : natural := 27; -- operand C select (0=IMM, 1=rs2)
|
constant ctrl_alu_opc_mux_c : natural := 27; -- operand C select (0=IMM, 1=rs2)
|
constant ctrl_alu_unsigned_c : natural := 28; -- is unsigned ALU operation
|
constant ctrl_alu_unsigned_c : natural := 28; -- is unsigned ALU operation
|
constant ctrl_alu_shift_dir_c : natural := 29; -- shift direction (0=left, 1=right)
|
constant ctrl_alu_shift_dir_c : natural := 29; -- shift direction (0=left, 1=right)
|
constant ctrl_alu_shift_ar_c : natural := 30; -- is arithmetic shift
|
constant ctrl_alu_shift_ar_c : natural := 30; -- is arithmetic shift
|
-- bus interface --
|
-- bus interface --
|
constant ctrl_bus_size_lsb_c : natural := 31; -- transfer size lsb (00=byte, 01=half-word)
|
constant ctrl_bus_size_lsb_c : natural := 31; -- transfer size lsb (00=byte, 01=half-word)
|
constant ctrl_bus_size_msb_c : natural := 32; -- transfer size msb (10=word, 11=?)
|
constant ctrl_bus_size_msb_c : natural := 32; -- transfer size msb (10=word, 11=?)
|
constant ctrl_bus_rd_c : natural := 33; -- read data request
|
constant ctrl_bus_rd_c : natural := 33; -- read data request
|
constant ctrl_bus_wr_c : natural := 34; -- write data request
|
constant ctrl_bus_wr_c : natural := 34; -- write data request
|
constant ctrl_bus_if_c : natural := 35; -- instruction fetch request (1: output PC, 0: output MAR)
|
constant ctrl_bus_if_c : natural := 35; -- instruction fetch request
|
constant ctrl_bus_mar_we_c : natural := 36; -- memory address register write enable
|
constant ctrl_bus_mar_we_c : natural := 36; -- memory address register write enable
|
constant ctrl_bus_mdo_we_c : natural := 37; -- memory data out register write enable
|
constant ctrl_bus_mdo_we_c : natural := 37; -- memory data out register write enable
|
constant ctrl_bus_mdi_we_c : natural := 38; -- memory data in register write enable
|
constant ctrl_bus_mdi_we_c : natural := 38; -- memory data in register write enable
|
constant ctrl_bus_unsigned_c : natural := 39; -- is unsigned load
|
constant ctrl_bus_unsigned_c : natural := 39; -- is unsigned load
|
constant ctrl_bus_exc_ack_c : natural := 40; -- acknowledge bus exception
|
constant ctrl_bus_ierr_ack_c : natural := 40; -- acknowledge instruction fetch bus exception
|
constant ctrl_bus_reset_c : natural := 41; -- reset bus unit, terminate all actions
|
constant ctrl_bus_derr_ack_c : natural := 41; -- acknowledge data access bus exception
|
|
constant ctrl_bus_fence_c : natural := 42; -- executed fence operation
|
|
constant ctrl_bus_fencei_c : natural := 43; -- executed fencei operation
|
-- co-processor --
|
-- co-processor --
|
constant ctrl_cp_use_c : natural := 42; -- is cp operation
|
constant ctrl_cp_use_c : natural := 44; -- is cp operation
|
constant ctrl_cp_id_lsb_c : natural := 43; -- cp select lsb
|
constant ctrl_cp_id_lsb_c : natural := 45; -- cp select lsb
|
constant ctrl_cp_id_msb_c : natural := 44; -- cp select msb
|
constant ctrl_cp_id_msb_c : natural := 46; -- cp select msb
|
constant ctrl_cp_cmd0_c : natural := 45; -- cp command bit 0
|
constant ctrl_cp_cmd0_c : natural := 47; -- cp command bit 0
|
constant ctrl_cp_cmd1_c : natural := 46; -- cp command bit 1
|
constant ctrl_cp_cmd1_c : natural := 48; -- cp command bit 1
|
constant ctrl_cp_cmd2_c : natural := 47; -- cp command bit 2
|
constant ctrl_cp_cmd2_c : natural := 49; -- cp command bit 2
|
-- control bus size --
|
-- control bus size --
|
constant ctrl_width_c : natural := 48; -- control bus size
|
constant ctrl_width_c : natural := 50; -- control bus size
|
|
|
-- ALU Comparator Bus ---------------------------------------------------------------------
|
-- ALU Comparator Bus ---------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant alu_cmp_equal_c : natural := 0;
|
constant alu_cmp_equal_c : natural := 0;
|
constant alu_cmp_less_c : natural := 1; -- for signed and unsigned comparisons
|
constant alu_cmp_less_c : natural := 1; -- for signed and unsigned comparisons
|
| Line 307... |
Line 313... |
constant alu_cmd_xor_c : std_ulogic_vector(2 downto 0) := "100"; -- r <= A xor B
|
constant alu_cmd_xor_c : std_ulogic_vector(2 downto 0) := "100"; -- r <= A xor B
|
constant alu_cmd_or_c : std_ulogic_vector(2 downto 0) := "101"; -- r <= A or B
|
constant alu_cmd_or_c : std_ulogic_vector(2 downto 0) := "101"; -- r <= A or B
|
constant alu_cmd_and_c : std_ulogic_vector(2 downto 0) := "110"; -- r <= A and B
|
constant alu_cmd_and_c : std_ulogic_vector(2 downto 0) := "110"; -- r <= A and B
|
constant alu_cmd_bitc_c : std_ulogic_vector(2 downto 0) := "111"; -- r <= A and (not B)
|
constant alu_cmd_bitc_c : std_ulogic_vector(2 downto 0) := "111"; -- r <= A and (not B)
|
|
|
|
-- Trap ID Codes --------------------------------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
constant trap_ima_c : std_ulogic_vector(4 downto 0) := "00000"; -- 0.0: instruction misaligned
|
|
constant trap_iba_c : std_ulogic_vector(4 downto 0) := "00001"; -- 0.1: instruction access fault
|
|
constant trap_iil_c : std_ulogic_vector(4 downto 0) := "00010"; -- 0.2: illegal instruction
|
|
constant trap_brk_c : std_ulogic_vector(4 downto 0) := "00011"; -- 0.3: breakpoint
|
|
constant trap_lma_c : std_ulogic_vector(4 downto 0) := "00100"; -- 0.4: load address misaligned
|
|
constant trap_lbe_c : std_ulogic_vector(4 downto 0) := "00101"; -- 0.5: load access fault
|
|
constant trap_sma_c : std_ulogic_vector(4 downto 0) := "00110"; -- 0.6: store address misaligned
|
|
constant trap_sbe_c : std_ulogic_vector(4 downto 0) := "00111"; -- 0.7: store access fault
|
|
constant trap_env_c : std_ulogic_vector(4 downto 0) := "01011"; -- 0.11: environment call from m-mode
|
|
constant trap_msi_c : std_ulogic_vector(4 downto 0) := "10011"; -- 1.3: machine software interrupt
|
|
constant trap_mti_c : std_ulogic_vector(4 downto 0) := "10111"; -- 1.7: machine timer interrupt
|
|
constant trap_mei_c : std_ulogic_vector(4 downto 0) := "11011"; -- 1.11: machine external interrupt
|
|
|
-- CPU Control Exception System -----------------------------------------------------------
|
-- CPU Control Exception System -----------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- exception source bits --
|
-- exception source bits --
|
constant exception_iaccess_c : natural := 0; -- instrution access fault
|
constant exception_iaccess_c : natural := 0; -- instrution access fault
|
constant exception_iillegal_c : natural := 1; -- illegal instrution
|
constant exception_iillegal_c : natural := 1; -- illegal instrution
|
| Line 321... |
Line 342... |
constant exception_lalign_c : natural := 6; -- load address misaligned
|
constant exception_lalign_c : natural := 6; -- load address misaligned
|
constant exception_saccess_c : natural := 7; -- store access fault
|
constant exception_saccess_c : natural := 7; -- store access fault
|
constant exception_laccess_c : natural := 8; -- load access fault
|
constant exception_laccess_c : natural := 8; -- load access fault
|
constant exception_width_c : natural := 9; -- length of this list in bits
|
constant exception_width_c : natural := 9; -- length of this list in bits
|
-- interrupt source bits --
|
-- interrupt source bits --
|
constant interrupt_mtime_irq_c : natural := 0; -- machine timer interrupt
|
constant interrupt_msw_irq_c : natural := 0; -- machine software interrupt
|
constant interrupt_msw_irq_c : natural := 1; -- machine sw interrupt
|
constant interrupt_mtime_irq_c : natural := 1; -- machine timer interrupt
|
constant interrupt_mext_irq_c : natural := 2; -- machine external interrupt
|
constant interrupt_mext_irq_c : natural := 2; -- machine external interrupt
|
constant interrupt_width_c : natural := 3; -- length of this list in bits
|
constant interrupt_width_c : natural := 3; -- length of this list in bits
|
|
|
-- Clock Generator -------------------------------------------------------------------------
|
-- Clock Generator -------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
| Line 343... |
Line 364... |
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_top
|
component neorv32_top
|
generic (
|
generic (
|
-- General --
|
-- General --
|
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
|
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
|
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
|
|
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
|
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
|
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
|
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
|
|
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_M : boolean := true; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M : boolean := true; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
| Line 393... |
Line 414... |
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
wb_stb_o : out std_ulogic; -- strobe
|
wb_stb_o : out std_ulogic; -- strobe
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge
|
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge
|
wb_err_i : in std_ulogic := '0'; -- transfer error
|
wb_err_i : in std_ulogic := '0'; -- transfer error
|
|
-- Advanced memory control signals (available if MEM_EXT_USE = true) --
|
|
fence_o : out std_ulogic; -- indicates an executed FENCE operation
|
|
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
|
-- GPIO --
|
-- GPIO --
|
gpio_o : out std_ulogic_vector(15 downto 0); -- parallel output
|
gpio_o : out std_ulogic_vector(15 downto 0); -- parallel output
|
gpio_i : in std_ulogic_vector(15 downto 0) := (others => '0'); -- parallel input
|
gpio_i : in std_ulogic_vector(15 downto 0) := (others => '0'); -- parallel input
|
-- UART --
|
-- UART --
|
uart_txd_o : out std_ulogic; -- UART send data
|
uart_txd_o : out std_ulogic; -- UART send data
|
| Line 420... |
Line 444... |
-- Component: CPU Top Entity --------------------------------------------------------------
|
-- Component: CPU Top Entity --------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_cpu
|
component neorv32_cpu
|
generic (
|
generic (
|
-- General --
|
-- General --
|
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
|
|
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
|
|
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
|
|
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
|
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
|
|
HW_THREAD_ID : std_ulogic_vector(31 downto 0):= x"00000000"; -- hardware thread id
|
|
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
|
-- Memory configuration: Instruction memory --
|
|
MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
|
|
MEM_ISPACE_SIZE : natural := 8*1024; -- total size of instruction memory space in byte
|
|
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
|
|
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
|
|
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
|
|
-- Memory configuration: Data memory --
|
|
MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space
|
|
MEM_DSPACE_SIZE : natural := 4*1024; -- total size of data memory space in byte
|
|
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
|
|
MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes
|
|
-- Memory configuration: External memory interface --
|
-- Memory configuration: External memory interface --
|
MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
|
MEM_EXT_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
|
MEM_EXT_TIMEOUT : natural := 15; -- cycles after which a valid bus access will timeout
|
|
-- Processor peripherals --
|
|
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
|
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
|
|
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
|
|
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
|
|
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
|
|
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
|
|
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
|
|
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)?
|
|
IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)?
|
|
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
|
|
);
|
);
|
port (
|
port (
|
-- global control --
|
-- global control --
|
clk_i : in std_ulogic; -- global clock, rising edge
|
clk_i : in std_ulogic; -- global clock, rising edge
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
-- bus interface --
|
-- instruction bus interface --
|
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
bus_we_o : out std_ulogic; -- write enable
|
i_bus_we_o : out std_ulogic; -- write enable
|
bus_re_o : out std_ulogic; -- read enable
|
i_bus_re_o : out std_ulogic; -- read enable
|
bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
bus_err_i : in std_ulogic; -- bus transfer error
|
i_bus_err_i : in std_ulogic; -- bus transfer error
|
|
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
|
|
-- data bus interface --
|
|
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
|
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
|
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
|
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
|
d_bus_we_o : out std_ulogic; -- write enable
|
|
d_bus_re_o : out std_ulogic; -- read enable
|
|
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
|
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
|
d_bus_err_i : in std_ulogic; -- bus transfer error
|
|
d_bus_fence_o : out std_ulogic; -- executed FENCE operation
|
-- system time input from MTIME --
|
-- system time input from MTIME --
|
time_i : in std_ulogic_vector(63 downto 0); -- current system time
|
time_i : in std_ulogic_vector(63 downto 0); -- current system time
|
-- external interrupts --
|
-- external interrupts --
|
|
msw_irq_i : in std_ulogic; -- software interrupt
|
clic_irq_i : in std_ulogic; -- CLIC interrupt request
|
clic_irq_i : in std_ulogic; -- CLIC interrupt request
|
mtime_irq_i : in std_ulogic -- machine timer interrupt
|
mtime_irq_i : in std_ulogic -- machine timer interrupt
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: CPU Control -----------------------------------------------------------------
|
-- Component: CPU Control -----------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_cpu_control
|
component neorv32_cpu_control
|
generic (
|
generic (
|
-- General --
|
-- General --
|
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
|
|
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
|
|
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
|
|
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
|
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
|
|
HW_THREAD_ID : std_ulogic_vector(31 downto 0):= x"00000000"; -- hardware thread id
|
|
CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := true -- implement instruction stream sync.?
|
-- Memory configuration: Instruction memory --
|
|
MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
|
|
MEM_ISPACE_SIZE : natural := 16*1024; -- total size of instruction memory space in byte
|
|
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
|
|
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
|
|
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
|
|
-- Memory configuration: Data memory --
|
|
MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space
|
|
MEM_DSPACE_SIZE : natural := 8*1024; -- total size of data memory space in byte
|
|
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
|
|
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
|
|
-- Memory configuration: External memory interface --
|
|
MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
|
|
-- Processor peripherals --
|
|
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
|
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
|
|
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
|
|
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
|
|
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
|
|
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
|
|
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
|
|
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)?
|
|
IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)?
|
|
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
|
|
);
|
);
|
port (
|
port (
|
-- global control --
|
-- global control --
|
clk_i : in std_ulogic; -- global clock, rising edge
|
clk_i : in std_ulogic; -- global clock, rising edge
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
ctrl_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
ctrl_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
-- status input --
|
-- status input --
|
alu_wait_i : in std_ulogic; -- wait for ALU
|
alu_wait_i : in std_ulogic; -- wait for ALU
|
bus_wait_i : in std_ulogic; -- wait for bus
|
bus_i_wait_i : in std_ulogic; -- wait for bus
|
|
bus_d_wait_i : in std_ulogic; -- wait for bus
|
-- data input --
|
-- data input --
|
instr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction
|
instr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction
|
cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status
|
cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status
|
alu_add_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU.add result
|
alu_add_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU.add result
|
-- data output --
|
-- data output --
|
| Line 539... |
Line 528... |
next_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- next PC (corresponding to current instruction)
|
next_pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- next PC (corresponding to current instruction)
|
-- csr interface --
|
-- csr interface --
|
csr_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR write data
|
csr_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR write data
|
csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
|
csr_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
|
-- external interrupt --
|
-- external interrupt --
|
|
msw_irq_i : in std_ulogic; -- software interrupt
|
clic_irq_i : in std_ulogic; -- CLIC interrupt request
|
clic_irq_i : in std_ulogic; -- CLIC interrupt request
|
mtime_irq_i : in std_ulogic; -- machine timer interrupt
|
mtime_irq_i : in std_ulogic; -- machine timer interrupt
|
-- system time input from MTIME --
|
-- system time input from MTIME --
|
time_i : in std_ulogic_vector(63 downto 0); -- current system time
|
time_i : in std_ulogic_vector(63 downto 0); -- current system time
|
-- bus access exceptions --
|
-- bus access exceptions --
|
| Line 550... |
Line 540... |
ma_instr_i : in std_ulogic; -- misaligned instruction address
|
ma_instr_i : in std_ulogic; -- misaligned instruction address
|
ma_load_i : in std_ulogic; -- misaligned load data address
|
ma_load_i : in std_ulogic; -- misaligned load data address
|
ma_store_i : in std_ulogic; -- misaligned store data address
|
ma_store_i : in std_ulogic; -- misaligned store data address
|
be_instr_i : in std_ulogic; -- bus error on instruction access
|
be_instr_i : in std_ulogic; -- bus error on instruction access
|
be_load_i : in std_ulogic; -- bus error on load data access
|
be_load_i : in std_ulogic; -- bus error on load data access
|
be_store_i : in std_ulogic; -- bus error on store data access
|
be_store_i : in std_ulogic -- bus error on store data access
|
bus_busy_i : in std_ulogic -- bus unit is busy
|
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: CPU Register File -----------------------------------------------------------
|
-- Component: CPU Register File -----------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
| Line 636... |
Line 625... |
port (
|
port (
|
-- global control --
|
-- global control --
|
clk_i : in std_ulogic; -- global clock, rising edge
|
clk_i : in std_ulogic; -- global clock, rising edge
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
|
-- data input --
|
-- cpu instruction fetch interface --
|
wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data
|
fetch_pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
|
pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- current PC
|
|
alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
|
|
-- data output --
|
|
instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction
|
instr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction
|
|
i_wait_o : out std_ulogic; -- wait for fetch to complete
|
|
--
|
|
ma_instr_o : out std_ulogic; -- misaligned instruction address
|
|
be_instr_o : out std_ulogic; -- bus error on instruction access
|
|
-- cpu data access interface --
|
|
addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result -> access address
|
|
wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data
|
rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
|
rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
|
-- status --
|
|
mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
|
mar_o : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
|
ma_instr_o : out std_ulogic; -- misaligned instruction address
|
d_wait_o : out std_ulogic; -- wait for access to complete
|
|
--
|
ma_load_o : out std_ulogic; -- misaligned load data address
|
ma_load_o : out std_ulogic; -- misaligned load data address
|
ma_store_o : out std_ulogic; -- misaligned store data address
|
ma_store_o : out std_ulogic; -- misaligned store data address
|
be_instr_o : out std_ulogic; -- bus error on instruction access
|
|
be_load_o : out std_ulogic; -- bus error on load data access
|
be_load_o : out std_ulogic; -- bus error on load data access
|
be_store_o : out std_ulogic; -- bus error on store data
|
be_store_o : out std_ulogic; -- bus error on store data access
|
bus_wait_o : out std_ulogic; -- wait for bus operation to finish
|
-- instruction bus --
|
bus_busy_o : out std_ulogic; -- bus unit is busy
|
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
-- bus system --
|
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
i_bus_we_o : out std_ulogic; -- write enable
|
bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
i_bus_re_o : out std_ulogic; -- read enable
|
bus_we_o : out std_ulogic; -- write enable
|
i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
bus_re_o : out std_ulogic; -- read enable
|
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
i_bus_err_i : in std_ulogic; -- bus transfer error
|
bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
i_bus_fence_o : out std_ulogic; -- fence operation
|
bus_err_i : in std_ulogic -- bus transfer error
|
-- data bus --
|
|
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
|
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
|
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
|
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
|
d_bus_we_o : out std_ulogic; -- write enable
|
|
d_bus_re_o : out std_ulogic; -- read enable
|
|
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
|
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
|
d_bus_err_i : in std_ulogic; -- bus transfer error
|
|
d_bus_fence_o : out std_ulogic -- fence operation
|
|
);
|
|
end component;
|
|
|
|
-- Component: CPU Bus Switch --------------------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
component neorv32_busswitch
|
|
generic (
|
|
PORT_CA_READ_ONLY : boolean := false; -- set if controller port A is read-only
|
|
PORT_CB_READ_ONLY : boolean := false -- set if controller port B is read-only
|
|
);
|
|
port (
|
|
-- global control --
|
|
clk_i : in std_ulogic; -- global clock, rising edge
|
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
|
-- controller interface a --
|
|
ca_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
|
ca_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
|
ca_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
|
ca_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
|
|
ca_bus_we_i : in std_ulogic; -- write enable
|
|
ca_bus_re_i : in std_ulogic; -- read enable
|
|
ca_bus_cancel_i : in std_ulogic; -- cancel current bus transaction
|
|
ca_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
|
|
ca_bus_err_o : out std_ulogic; -- bus transfer error
|
|
-- controller interface b --
|
|
cb_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
|
cb_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
|
cb_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
|
cb_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
|
|
cb_bus_we_i : in std_ulogic; -- write enable
|
|
cb_bus_re_i : in std_ulogic; -- read enable
|
|
cb_bus_cancel_i : in std_ulogic; -- cancel current bus transaction
|
|
cb_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
|
|
cb_bus_err_o : out std_ulogic; -- bus transfer error
|
|
-- peripheral bus --
|
|
p_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
|
p_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
|
p_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
|
p_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
|
p_bus_we_o : out std_ulogic; -- write enable
|
|
p_bus_re_o : out std_ulogic; -- read enable
|
|
p_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
|
p_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
|
p_bus_err_i : in std_ulogic -- bus transfer error
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: CPU Compressed Instructions Decompressor ------------------------------------
|
-- Component: CPU Compressed Instructions Decompressor ------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
| Line 987... |
Line 1033... |
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
ack_o : out std_ulogic -- transfer acknowledge
|
ack_o : out std_ulogic -- transfer acknowledge
|
);
|
);
|
end component;
|
end component;
|
|
|
|
---- Component: System Configuration Information Memory (SYSINFO) ---------------------------
|
|
---- -------------------------------------------------------------------------------------------
|
|
component neorv32_sysinfo
|
|
generic (
|
|
-- General --
|
|
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
|
|
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
|
|
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
|
|
-- Memory configuration: Instruction memory --
|
|
MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
|
|
MEM_ISPACE_SIZE : natural := 8*1024; -- total size of instruction memory space in byte
|
|
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
|
|
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
|
|
MEM_INT_IMEM_ROM : boolean := false; -- implement processor-internal instruction memory as ROM
|
|
-- Memory configuration: Data memory --
|
|
MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space
|
|
MEM_DSPACE_SIZE : natural := 4*1024; -- total size of data memory space in byte
|
|
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
|
|
MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes
|
|
-- Memory configuration: External memory interface --
|
|
MEM_EXT_USE : boolean := false; -- implement external memory bus interface?
|
|
-- Processor peripherals --
|
|
IO_GPIO_USE : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
|
IO_MTIME_USE : boolean := true; -- implement machine system timer (MTIME)?
|
|
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
|
|
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
|
|
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
|
|
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
|
|
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
|
|
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)?
|
|
IO_TRNG_USE : boolean := true; -- implement true random number generator (TRNG)?
|
|
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
|
|
);
|
|
port (
|
|
-- host access --
|
|
clk_i : in std_ulogic; -- global clock line
|
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
|
rden_i : in std_ulogic; -- read enable
|
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
|
ack_o : out std_ulogic -- transfer acknowledge
|
|
);
|
|
end component;
|
|
|
end neorv32_package;
|
end neorv32_package;
|
|
|
package body neorv32_package is
|
package body neorv32_package is
|
|
|
-- Function: Minimal required bit width ---------------------------------------------------
|
-- Function: Minimal required bit width ---------------------------------------------------
|
